Low Cost Hardware Back Propagation Algorithm

The first successful implementation of Artificial Neural Networks (ANNs) was published a little over a decade ago. It is time to review the progress that has been made in this research area. This paper provides taxonomy for classifying Field Programmable Gate Arrays (FPGAs) implementation of ANNs. D...

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Autor principal: Ammar A. Hassan
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Lenguaje:EN
Publicado: Al-Khwarizmi College of Engineering – University of Baghdad 2007
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Acceso en línea:https://doaj.org/article/cc163f6fc02f4850885e861cb0298b82
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spelling oai:doaj.org-article:cc163f6fc02f4850885e861cb0298b822021-12-02T04:55:13ZLow Cost Hardware Back Propagation Algorithm1818-1171https://doaj.org/article/cc163f6fc02f4850885e861cb0298b822007-01-01T00:00:00Zhttp://www.iasj.net/iasj?func=fulltext&aId=2288https://doaj.org/toc/1818-1171The first successful implementation of Artificial Neural Networks (ANNs) was published a little over a decade ago. It is time to review the progress that has been made in this research area. This paper provides taxonomy for classifying Field Programmable Gate Arrays (FPGAs) implementation of ANNs. Different implementation techniques and design issues are discussed, such as obtaining a suitable activation function and numerical truncation technique trade-off, the improvement of the learning algorithm to reduce the cost of neuron and in result the total cost and the total speed of the complete ANN. Finally, the implementation of a complete very fast circuit for the pattern of English Digit Numbers NN has four layers of 70 nodes (neurons) on single chip using Xilinx FPGA technique is given.The main goal of this paper is how to achieve the suitable activation function and weights for this network that gives minimum hardware cost when all stages of this ANN algorithm is implemented on FPGAAmmar A. HassanAl-Khwarizmi College of Engineering – University of BaghdadarticleChemical engineeringTP155-156Engineering (General). Civil engineering (General)TA1-2040ENAl-Khawarizmi Engineering Journal, Vol 3, Iss 1, Pp 81-90 (2007)
institution DOAJ
collection DOAJ
language EN
topic Chemical engineering
TP155-156
Engineering (General). Civil engineering (General)
TA1-2040
spellingShingle Chemical engineering
TP155-156
Engineering (General). Civil engineering (General)
TA1-2040
Ammar A. Hassan
Low Cost Hardware Back Propagation Algorithm
description The first successful implementation of Artificial Neural Networks (ANNs) was published a little over a decade ago. It is time to review the progress that has been made in this research area. This paper provides taxonomy for classifying Field Programmable Gate Arrays (FPGAs) implementation of ANNs. Different implementation techniques and design issues are discussed, such as obtaining a suitable activation function and numerical truncation technique trade-off, the improvement of the learning algorithm to reduce the cost of neuron and in result the total cost and the total speed of the complete ANN. Finally, the implementation of a complete very fast circuit for the pattern of English Digit Numbers NN has four layers of 70 nodes (neurons) on single chip using Xilinx FPGA technique is given.The main goal of this paper is how to achieve the suitable activation function and weights for this network that gives minimum hardware cost when all stages of this ANN algorithm is implemented on FPGA
format article
author Ammar A. Hassan
author_facet Ammar A. Hassan
author_sort Ammar A. Hassan
title Low Cost Hardware Back Propagation Algorithm
title_short Low Cost Hardware Back Propagation Algorithm
title_full Low Cost Hardware Back Propagation Algorithm
title_fullStr Low Cost Hardware Back Propagation Algorithm
title_full_unstemmed Low Cost Hardware Back Propagation Algorithm
title_sort low cost hardware back propagation algorithm
publisher Al-Khwarizmi College of Engineering – University of Baghdad
publishDate 2007
url https://doaj.org/article/cc163f6fc02f4850885e861cb0298b82
work_keys_str_mv AT ammarahassan lowcosthardwarebackpropagationalgorithm
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