Utilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks

A novel design method using unsigned input is proposed for a high-density and parallel synaptic string architecture capable of bit-wise operation and bit-counting utilizing NAND flash memory. Though the NAND flash memory has a cell string structure, unsigned binary input enables analogue and paralle...

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Autores principales:	Sung-Tae Lee, Gyuho Yeom, Joon Hwang, Hyeongsu Kim, Honam Yoo, Byung-Gook Park, Jong-Ho Lee
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	In-memory computing neuromorphic binary neural networks synaptic device hardware neural network deep neural network Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/d77a260ec6664266a98cff0c91cac7c1
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id	oai:doaj.org-article:d77a260ec6664266a98cff0c91cac7c1
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spelling	oai:doaj.org-article:d77a260ec6664266a98cff0c91cac7c12021-11-10T00:00:23ZUtilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks2168-673410.1109/JEDS.2021.3123632https://doaj.org/article/d77a260ec6664266a98cff0c91cac7c12021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9592625/https://doaj.org/toc/2168-6734A novel design method using unsigned input is proposed for a high-density and parallel synaptic string architecture capable of bit-wise operation and bit-counting utilizing NAND flash memory. Though the NAND flash memory has a cell string structure, unsigned binary input enables analogue and parallel bit-counting in NAND flash memory, while achieving high accuracy comparable to that of signed input. Adopting unsigned input allows using current sense amplifier as neuron circuit, which reduces burden of peripheral circuits. In addition, the operation scheme for convolution layers is proposed for parallel convolution operation utilizing NAND flash memory. We show that sufficiently low device variation of 7.2 % obtained by applying 1 erase or program pulse achieves accuracy of 98.12 % and 87.12 % for MNIST and CIFAR 10 patterns, respectively.Sung-Tae LeeGyuho YeomJoon HwangHyeongsu KimHonam YooByung-Gook ParkJong-Ho LeeIEEEarticleIn-memory computingneuromorphicbinary neural networkssynaptic devicehardware neural networkdeep neural networkElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Journal of the Electron Devices Society, Vol 9, Pp 1049-1054 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	In-memory computing neuromorphic binary neural networks synaptic device hardware neural network deep neural network Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	In-memory computing neuromorphic binary neural networks synaptic device hardware neural network deep neural network Electrical engineering. Electronics. Nuclear engineering TK1-9971 Sung-Tae Lee Gyuho Yeom Joon Hwang Hyeongsu Kim Honam Yoo Byung-Gook Park Jong-Ho Lee Utilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks
description	A novel design method using unsigned input is proposed for a high-density and parallel synaptic string architecture capable of bit-wise operation and bit-counting utilizing NAND flash memory. Though the NAND flash memory has a cell string structure, unsigned binary input enables analogue and parallel bit-counting in NAND flash memory, while achieving high accuracy comparable to that of signed input. Adopting unsigned input allows using current sense amplifier as neuron circuit, which reduces burden of peripheral circuits. In addition, the operation scheme for convolution layers is proposed for parallel convolution operation utilizing NAND flash memory. We show that sufficiently low device variation of 7.2 % obtained by applying 1 erase or program pulse achieves accuracy of 98.12 % and 87.12 % for MNIST and CIFAR 10 patterns, respectively.
format	article
author	Sung-Tae Lee Gyuho Yeom Joon Hwang Hyeongsu Kim Honam Yoo Byung-Gook Park Jong-Ho Lee
author_facet	Sung-Tae Lee Gyuho Yeom Joon Hwang Hyeongsu Kim Honam Yoo Byung-Gook Park Jong-Ho Lee
author_sort	Sung-Tae Lee
title	Utilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks
title_short	Utilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks
title_full	Utilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks
title_fullStr	Utilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks
title_full_unstemmed	Utilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks
title_sort	utilization of unsigned inputs for nand flash-based parallel and high-density synaptic architecture in binary neural networks
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/d77a260ec6664266a98cff0c91cac7c1
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_version_	1718440792643600384

Utilization of Unsigned Inputs for NAND Flash-Based Parallel and High-Density Synaptic Architecture in Binary Neural Networks

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