Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity

A set of efficient algorithmic solutions suitable to the fully parallel hardware implementation of the short-length circular convolution cores is proposed. The advantage of the presented algorithms is that they require significantly fewer multiplications as compared to the naive method of implementi...

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Autores principales:	Aleksandr Cariow, Janusz P. Paplinski
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	digital signal processing circular convolution resource-efficient algorithms Electronics TK7800-8360
Acceso en línea:	https://doaj.org/article/dd4c21f4850d42aca58e2856f584452d
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spelling	oai:doaj.org-article:dd4c21f4850d42aca58e2856f584452d2021-11-25T17:24:45ZAlgorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity10.3390/electronics102228002079-9292https://doaj.org/article/dd4c21f4850d42aca58e2856f584452d2021-11-01T00:00:00Zhttps://www.mdpi.com/2079-9292/10/22/2800https://doaj.org/toc/2079-9292A set of efficient algorithmic solutions suitable to the fully parallel hardware implementation of the short-length circular convolution cores is proposed. The advantage of the presented algorithms is that they require significantly fewer multiplications as compared to the naive method of implementing this operation. During the synthesis of the presented algorithms, the matrix notation of the cyclic convolution operation was used, which made it possible to represent this operation using the matrix–vector product. The fact that the matrix multiplicand is a circulant matrix allows its successful factorization, which leads to a decrease in the number of multiplications when calculating such a product. The proposed algorithms are oriented towards a completely parallel hardware implementation, but in comparison with a naive approach to a completely parallel hardware implementation, they require a significantly smaller number of hardwired multipliers. Since the wired multiplier occupies a much larger area on the VLSI and consumes more power than the wired adder, the proposed solutions are resource efficient and energy efficient in terms of their hardware implementation. We considered circular convolutions for sequences of lengths <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>N</mi><mo>=</mo></mrow></semantics></math></inline-formula> 2, 3, 4, 5, 6, 7, 8, and 9.Aleksandr CariowJanusz P. PaplinskiMDPI AGarticledigital signal processingcircular convolutionresource-efficient algorithmsElectronicsTK7800-8360ENElectronics, Vol 10, Iss 2800, p 2800 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	digital signal processing circular convolution resource-efficient algorithms Electronics TK7800-8360
spellingShingle	digital signal processing circular convolution resource-efficient algorithms Electronics TK7800-8360 Aleksandr Cariow Janusz P. Paplinski Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity
description	A set of efficient algorithmic solutions suitable to the fully parallel hardware implementation of the short-length circular convolution cores is proposed. The advantage of the presented algorithms is that they require significantly fewer multiplications as compared to the naive method of implementing this operation. During the synthesis of the presented algorithms, the matrix notation of the cyclic convolution operation was used, which made it possible to represent this operation using the matrix–vector product. The fact that the matrix multiplicand is a circulant matrix allows its successful factorization, which leads to a decrease in the number of multiplications when calculating such a product. The proposed algorithms are oriented towards a completely parallel hardware implementation, but in comparison with a naive approach to a completely parallel hardware implementation, they require a significantly smaller number of hardwired multipliers. Since the wired multiplier occupies a much larger area on the VLSI and consumes more power than the wired adder, the proposed solutions are resource efficient and energy efficient in terms of their hardware implementation. We considered circular convolutions for sequences of lengths <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>N</mi><mo>=</mo></mrow></semantics></math></inline-formula> 2, 3, 4, 5, 6, 7, 8, and 9.
format	article
author	Aleksandr Cariow Janusz P. Paplinski
author_facet	Aleksandr Cariow Janusz P. Paplinski
author_sort	Aleksandr Cariow
title	Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity
title_short	Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity
title_full	Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity
title_fullStr	Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity
title_full_unstemmed	Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity
title_sort	algorithmic structures for realizing short-length circular convolutions with reduced complexity
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/dd4c21f4850d42aca58e2856f584452d
work_keys_str_mv	AT aleksandrcariow algorithmicstructuresforrealizingshortlengthcircularconvolutionswithreducedcomplexity AT januszppaplinski algorithmicstructuresforrealizingshortlengthcircularconvolutionswithreducedcomplexity
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Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity

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