High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

Abstract Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/...

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Autores principales:	Tsung-Ta Wu, Wen-Hsien Huang, Chih-Chao Yang, Hung-Chun Chen, Tung-Ying Hsieh, Wei-Sheng Lin, Ming-Hsuan Kao, Chiu-Hao Chen, Jie-Yi Yao, Yi-Ling Jian, Chiung-Chih Hsu, Kun-Lin Lin, Chang-Hong Shen, Yu-Lun Chueh, Jia-Min Shieh
Formato:	article
Lenguaje:	EN
Publicado:	Nature Portfolio 2017
Materias:	Medicine R Science Q
Acceso en línea:	https://doaj.org/article/dfca7c0d50a149839d75f7508a8ac08d
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spelling	oai:doaj.org-article:dfca7c0d50a149839d75f7508a8ac08d2021-12-02T15:06:20ZHigh Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits10.1038/s41598-017-01012-y2045-2322https://doaj.org/article/dfca7c0d50a149839d75f7508a8ac08d2017-05-01T00:00:00Zhttps://doi.org/10.1038/s41598-017-01012-yhttps://doaj.org/toc/2045-2322Abstract Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.Tsung-Ta WuWen-Hsien HuangChih-Chao YangHung-Chun ChenTung-Ying HsiehWei-Sheng LinMing-Hsuan KaoChiu-Hao ChenJie-Yi YaoYi-Ling JianChiung-Chih HsuKun-Lin LinChang-Hong ShenYu-Lun ChuehJia-Min ShiehNature PortfolioarticleMedicineRScienceQENScientific Reports, Vol 7, Iss 1, Pp 1-11 (2017)
institution	DOAJ
collection	DOAJ
language	EN
topic	Medicine R Science Q
spellingShingle	Medicine R Science Q Tsung-Ta Wu Wen-Hsien Huang Chih-Chao Yang Hung-Chun Chen Tung-Ying Hsieh Wei-Sheng Lin Ming-Hsuan Kao Chiu-Hao Chen Jie-Yi Yao Yi-Ling Jian Chiung-Chih Hsu Kun-Lin Lin Chang-Hong Shen Yu-Lun Chueh Jia-Min Shieh High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
description	Abstract Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.
format	article
author	Tsung-Ta Wu Wen-Hsien Huang Chih-Chao Yang Hung-Chun Chen Tung-Ying Hsieh Wei-Sheng Lin Ming-Hsuan Kao Chiu-Hao Chen Jie-Yi Yao Yi-Ling Jian Chiung-Chih Hsu Kun-Lin Lin Chang-Hong Shen Yu-Lun Chueh Jia-Min Shieh
author_facet	Tsung-Ta Wu Wen-Hsien Huang Chih-Chao Yang Hung-Chun Chen Tung-Ying Hsieh Wei-Sheng Lin Ming-Hsuan Kao Chiu-Hao Chen Jie-Yi Yao Yi-Ling Jian Chiung-Chih Hsu Kun-Lin Lin Chang-Hong Shen Yu-Lun Chueh Jia-Min Shieh
author_sort	Tsung-Ta Wu
title	High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
title_short	High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
title_full	High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
title_fullStr	High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
title_full_unstemmed	High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
title_sort	high performance and low power monolithic three-dimensional sub-50 nm poly si thin film transistor (tfts) circuits
publisher	Nature Portfolio
publishDate	2017
url	https://doaj.org/article/dfca7c0d50a149839d75f7508a8ac08d
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High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

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