A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory
With the immense increase in the processing data during the scaling down of semiconductor devices by Moore’s Law, it is in urgent need to use data analytics to meet the state of the art performance in both manufacturing and device compact modeling. In particular, managing the fabrication...
Guardado en:
| Autores principales: | , , , , , , , |
|---|---|
| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
IEEE
2021
|
| Materias: | |
| Acceso en línea: | https://doaj.org/article/e1529a89857f43f3ad53da5da0aca59b |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
| id |
oai:doaj.org-article:e1529a89857f43f3ad53da5da0aca59b |
|---|---|
| record_format |
dspace |
| spelling |
oai:doaj.org-article:e1529a89857f43f3ad53da5da0aca59b2021-11-18T00:00:46ZA Process-Aware Memory Compact-Device Model Using Long-Short Term Memory2169-353610.1109/ACCESS.2020.3047491https://doaj.org/article/e1529a89857f43f3ad53da5da0aca59b2021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9308977/https://doaj.org/toc/2169-3536With the immense increase in the processing data during the scaling down of semiconductor devices by Moore’s Law, it is in urgent need to use data analytics to meet the state of the art performance in both manufacturing and device compact modeling. In particular, managing the fabrication cost and promptly providing compact device models, especially for new or emerging devices, is challenging. To ease out these issues, we propose a unified, general-purpose, process-aware machine learning (ML) based compact model (CM) for resistive random-access memory (RRAM), and the same methodology can be used for any memory devices with hysteresis. A long short-term memory (LSTM) ML model is used to fit the RRAM current-voltage (I-V) characteristics. The memorizing capability of LSTM ensures one model can fit both RRAM low resistance state (LRS) and high resistance state (HRS). The fitted dataset is based on the fabricated RRAM samples using TaN/HfO<sub>2</sub>/Pt/Ti/SiO<sub>2</sub>/Si structure. The resultant fitting error is 0.0096 in sinusoidal wave input voltage and 0.0148 in random walk voltage sequences. In the process-aware demonstration, we use post-oxide annealing dataset from 300°C to 500°C. The root mean squared error (RMSE) in the process-aware RRAM compact model is 0.0028. Thus, the LSTM-based CM has the potential to compete with the conventional compact device models in terms of shorter developing time, better fitting capability in emerging devices and a large number of devices, easily incorporated process-aware models, and one unified model accounting for LRS and HRS ensuring differentiability. We propose that the LSTM based memory CM can be useful in intelligent manufacturing, process tuning, and simulation program with integrated circuit emphasis (SPICE) modeling in circuit simulation.Albert S. LinSparsh PratikJun OtaTejender Singh RawatTzu-Hsiang HuangChun-Ling HsuWei-Ming SuTseung-Yuen TsengIEEEarticleIntelligent manufacturing systemsmachine learningprocess aware modelingRRAMsemiconductor process modelingElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Access, Vol 9, Pp 3126-3139 (2021) |
| institution |
DOAJ |
| collection |
DOAJ |
| language |
EN |
| topic |
Intelligent manufacturing systems machine learning process aware modeling RRAM semiconductor process modeling Electrical engineering. Electronics. Nuclear engineering TK1-9971 |
| spellingShingle |
Intelligent manufacturing systems machine learning process aware modeling RRAM semiconductor process modeling Electrical engineering. Electronics. Nuclear engineering TK1-9971 Albert S. Lin Sparsh Pratik Jun Ota Tejender Singh Rawat Tzu-Hsiang Huang Chun-Ling Hsu Wei-Ming Su Tseung-Yuen Tseng A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory |
| description |
With the immense increase in the processing data during the scaling down of semiconductor devices by Moore’s Law, it is in urgent need to use data analytics to meet the state of the art performance in both manufacturing and device compact modeling. In particular, managing the fabrication cost and promptly providing compact device models, especially for new or emerging devices, is challenging. To ease out these issues, we propose a unified, general-purpose, process-aware machine learning (ML) based compact model (CM) for resistive random-access memory (RRAM), and the same methodology can be used for any memory devices with hysteresis. A long short-term memory (LSTM) ML model is used to fit the RRAM current-voltage (I-V) characteristics. The memorizing capability of LSTM ensures one model can fit both RRAM low resistance state (LRS) and high resistance state (HRS). The fitted dataset is based on the fabricated RRAM samples using TaN/HfO<sub>2</sub>/Pt/Ti/SiO<sub>2</sub>/Si structure. The resultant fitting error is 0.0096 in sinusoidal wave input voltage and 0.0148 in random walk voltage sequences. In the process-aware demonstration, we use post-oxide annealing dataset from 300°C to 500°C. The root mean squared error (RMSE) in the process-aware RRAM compact model is 0.0028. Thus, the LSTM-based CM has the potential to compete with the conventional compact device models in terms of shorter developing time, better fitting capability in emerging devices and a large number of devices, easily incorporated process-aware models, and one unified model accounting for LRS and HRS ensuring differentiability. We propose that the LSTM based memory CM can be useful in intelligent manufacturing, process tuning, and simulation program with integrated circuit emphasis (SPICE) modeling in circuit simulation. |
| format |
article |
| author |
Albert S. Lin Sparsh Pratik Jun Ota Tejender Singh Rawat Tzu-Hsiang Huang Chun-Ling Hsu Wei-Ming Su Tseung-Yuen Tseng |
| author_facet |
Albert S. Lin Sparsh Pratik Jun Ota Tejender Singh Rawat Tzu-Hsiang Huang Chun-Ling Hsu Wei-Ming Su Tseung-Yuen Tseng |
| author_sort |
Albert S. Lin |
| title |
A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory |
| title_short |
A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory |
| title_full |
A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory |
| title_fullStr |
A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory |
| title_full_unstemmed |
A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory |
| title_sort |
process-aware memory compact-device model using long-short term memory |
| publisher |
IEEE |
| publishDate |
2021 |
| url |
https://doaj.org/article/e1529a89857f43f3ad53da5da0aca59b |
| work_keys_str_mv |
AT albertslin aprocessawarememorycompactdevicemodelusinglongshorttermmemory AT sparshpratik aprocessawarememorycompactdevicemodelusinglongshorttermmemory AT junota aprocessawarememorycompactdevicemodelusinglongshorttermmemory AT tejendersinghrawat aprocessawarememorycompactdevicemodelusinglongshorttermmemory AT tzuhsianghuang aprocessawarememorycompactdevicemodelusinglongshorttermmemory AT chunlinghsu aprocessawarememorycompactdevicemodelusinglongshorttermmemory AT weimingsu aprocessawarememorycompactdevicemodelusinglongshorttermmemory AT tseungyuentseng aprocessawarememorycompactdevicemodelusinglongshorttermmemory AT albertslin processawarememorycompactdevicemodelusinglongshorttermmemory AT sparshpratik processawarememorycompactdevicemodelusinglongshorttermmemory AT junota processawarememorycompactdevicemodelusinglongshorttermmemory AT tejendersinghrawat processawarememorycompactdevicemodelusinglongshorttermmemory AT tzuhsianghuang processawarememorycompactdevicemodelusinglongshorttermmemory AT chunlinghsu processawarememorycompactdevicemodelusinglongshorttermmemory AT weimingsu processawarememorycompactdevicemodelusinglongshorttermmemory AT tseungyuentseng processawarememorycompactdevicemodelusinglongshorttermmemory |
| _version_ |
1718425256063926272 |