A High speed data link optimization for digitalized transfer to processing FPGA
State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individu...
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| Autores principales: | , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
EDP Sciences
2021
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/e178805670524518bd976e3868ba9818 |
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| Sumario: | State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individual detectors, may not exhaust the capabilities of a single FPGA transceiver input.
The preprocessing is usually carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data rates, optimizing simultaneously the use of the FPGA resources, is the topic of the present work.
We have developed a solution based on the Time Domain Multiplexing link aggregation, in the form of a Mezzanine board. This mezzanine combines four channels from an optical or copper input up to 2.5 Gbps to one up to 10Gbps, and serves them to the FPGA via the mezzanine connector. The board itself is controlled by a small FPGA by the Two Wire Interface (TWI) protocol as a standalone intelligent device, so minimum slow control is needed. The solution has been also developed for a motherboard housing a SoM module and FMC connector as an alternative implementation. An associated firmware has been developed to de-aggregate the data in the FPGA and recover the original sampled data, based on JESD204 communication protocol, inside the FPGA. The method has been validated and applications, beyond the development of the AGATA electronics, may be envisioned. |
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