A High speed data link optimization for digitalized transfer to processing FPGA

State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individu...

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Autores principales:	Collado J., Gonzalez V., Gadea A.
Formato:	article
Lenguaje:	EN
Publicado:	EDP Sciences 2021
Materias:	fpga optimization time domain multiplexing communication serial link electronic instrumentation Physics QC1-999
Acceso en línea:	https://doaj.org/article/e178805670524518bd976e3868ba9818
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spelling	oai:doaj.org-article:e178805670524518bd976e3868ba98182021-12-02T17:12:45ZA High speed data link optimization for digitalized transfer to processing FPGA2100-014X10.1051/epjconf/202125301006https://doaj.org/article/e178805670524518bd976e3868ba98182021-01-01T00:00:00Zhttps://www.epj-conferences.org/articles/epjconf/pdf/2021/07/epjconf_animma2021_01006.pdfhttps://doaj.org/toc/2100-014XState-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individual detectors, may not exhaust the capabilities of a single FPGA transceiver input. The preprocessing is usually carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data rates, optimizing simultaneously the use of the FPGA resources, is the topic of the present work. We have developed a solution based on the Time Domain Multiplexing link aggregation, in the form of a Mezzanine board. This mezzanine combines four channels from an optical or copper input up to 2.5 Gbps to one up to 10Gbps, and serves them to the FPGA via the mezzanine connector. The board itself is controlled by a small FPGA by the Two Wire Interface (TWI) protocol as a standalone intelligent device, so minimum slow control is needed. The solution has been also developed for a motherboard housing a SoM module and FMC connector as an alternative implementation. An associated firmware has been developed to de-aggregate the data in the FPGA and recover the original sampled data, based on JESD204 communication protocol, inside the FPGA. The method has been validated and applications, beyond the development of the AGATA electronics, may be envisioned.Collado J.Gonzalez V.Gadea A.EDP Sciencesarticlefpga optimizationtime domain multiplexingcommunication serial linkelectronic instrumentationPhysicsQC1-999ENEPJ Web of Conferences, Vol 253, p 01006 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	fpga optimization time domain multiplexing communication serial link electronic instrumentation Physics QC1-999
spellingShingle	fpga optimization time domain multiplexing communication serial link electronic instrumentation Physics QC1-999 Collado J. Gonzalez V. Gadea A. A High speed data link optimization for digitalized transfer to processing FPGA
description	State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individual detectors, may not exhaust the capabilities of a single FPGA transceiver input. The preprocessing is usually carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data rates, optimizing simultaneously the use of the FPGA resources, is the topic of the present work. We have developed a solution based on the Time Domain Multiplexing link aggregation, in the form of a Mezzanine board. This mezzanine combines four channels from an optical or copper input up to 2.5 Gbps to one up to 10Gbps, and serves them to the FPGA via the mezzanine connector. The board itself is controlled by a small FPGA by the Two Wire Interface (TWI) protocol as a standalone intelligent device, so minimum slow control is needed. The solution has been also developed for a motherboard housing a SoM module and FMC connector as an alternative implementation. An associated firmware has been developed to de-aggregate the data in the FPGA and recover the original sampled data, based on JESD204 communication protocol, inside the FPGA. The method has been validated and applications, beyond the development of the AGATA electronics, may be envisioned.
format	article
author	Collado J. Gonzalez V. Gadea A.
author_facet	Collado J. Gonzalez V. Gadea A.
author_sort	Collado J.
title	A High speed data link optimization for digitalized transfer to processing FPGA
title_short	A High speed data link optimization for digitalized transfer to processing FPGA
title_full	A High speed data link optimization for digitalized transfer to processing FPGA
title_fullStr	A High speed data link optimization for digitalized transfer to processing FPGA
title_full_unstemmed	A High speed data link optimization for digitalized transfer to processing FPGA
title_sort	high speed data link optimization for digitalized transfer to processing fpga
publisher	EDP Sciences
publishDate	2021
url	https://doaj.org/article/e178805670524518bd976e3868ba9818
work_keys_str_mv	AT colladoj ahighspeeddatalinkoptimizationfordigitalizedtransfertoprocessingfpga AT gonzalezv ahighspeeddatalinkoptimizationfordigitalizedtransfertoprocessingfpga AT gadeaa ahighspeeddatalinkoptimizationfordigitalizedtransfertoprocessingfpga AT colladoj highspeeddatalinkoptimizationfordigitalizedtransfertoprocessingfpga AT gonzalezv highspeeddatalinkoptimizationfordigitalizedtransfertoprocessingfpga AT gadeaa highspeeddatalinkoptimizationfordigitalizedtransfertoprocessingfpga
_version_	1718381411990241280

A High speed data link optimization for digitalized transfer to processing FPGA

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