Reduction of the error in the hardware neural network

Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs) o...

Descripción completa

Guardado en:

Detalles Bibliográficos
Autor principal:	Dhafer r. Zaghar
Formato:	article
Lenguaje:	EN
Publicado:	Al-Khwarizmi College of Engineering – University of Baghdad 2007
Materias:	Neural co-processor DSP FPGA ISE 4.1i software adder multiplier. Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040
Acceso en línea:	https://doaj.org/article/edc8f4f44bc4479e9ec2bd8dd4b88469
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

id	oai:doaj.org-article:edc8f4f44bc4479e9ec2bd8dd4b88469
record_format	dspace
spelling	oai:doaj.org-article:edc8f4f44bc4479e9ec2bd8dd4b884692021-12-02T05:41:53ZReduction of the error in the hardware neural network1818-1171https://doaj.org/article/edc8f4f44bc4479e9ec2bd8dd4b884692007-01-01T00:00:00Zhttp://www.iasj.net/iasj?func=fulltext&aId=2338https://doaj.org/toc/1818-1171Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs) offer the required flexibility and fast design-to-implementation time with the possibility of exploiting highly parallel computations like those required by ANNs in hardware. The bounded width of the data in FPGA ANNs will add an additional error to the result of the output. This paper derives the equations of the additional error value that generate from bounded width of the data and proposed a method to reduce the effect of the error to give an optimal result in the output with a low cost.Dhafer r. ZagharAl-Khwarizmi College of Engineering – University of BaghdadarticleNeuralco-processorDSPFPGAISE 4.1i softwareaddermultiplier.Chemical engineeringTP155-156Engineering (General). Civil engineering (General)TA1-2040ENAl-Khawarizmi Engineering Journal, Vol 3, Iss 2, Pp 1-7 (2007)
institution	DOAJ
collection	DOAJ
language	EN
topic	Neural co-processor DSP FPGA ISE 4.1i software adder multiplier. Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040
spellingShingle	Neural co-processor DSP FPGA ISE 4.1i software adder multiplier. Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040 Dhafer r. Zaghar Reduction of the error in the hardware neural network
description	Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs) offer the required flexibility and fast design-to-implementation time with the possibility of exploiting highly parallel computations like those required by ANNs in hardware. The bounded width of the data in FPGA ANNs will add an additional error to the result of the output. This paper derives the equations of the additional error value that generate from bounded width of the data and proposed a method to reduce the effect of the error to give an optimal result in the output with a low cost.
format	article
author	Dhafer r. Zaghar
author_facet	Dhafer r. Zaghar
author_sort	Dhafer r. Zaghar
title	Reduction of the error in the hardware neural network
title_short	Reduction of the error in the hardware neural network
title_full	Reduction of the error in the hardware neural network
title_fullStr	Reduction of the error in the hardware neural network
title_full_unstemmed	Reduction of the error in the hardware neural network
title_sort	reduction of the error in the hardware neural network
publisher	Al-Khwarizmi College of Engineering – University of Baghdad
publishDate	2007
url	https://doaj.org/article/edc8f4f44bc4479e9ec2bd8dd4b88469
work_keys_str_mv	AT dhaferrzaghar reductionoftheerrorinthehardwareneuralnetwork
_version_	1718400267137843200

Reduction of the error in the hardware neural network

Ejemplares similares