Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultra-high Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimiz...

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Autores principales:	Zijian Zhao, Yao Zhou, Hao Zhu, Qingqing Sun, David Wei Zhang
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	MCU gate oxide static power consumption gate leakage Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/f06ea28a616943c38fa53f2f9bcfa7c3
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id	oai:doaj.org-article:f06ea28a616943c38fa53f2f9bcfa7c3
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spelling	oai:doaj.org-article:f06ea28a616943c38fa53f2f9bcfa7c32021-11-18T00:00:38ZGate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications2168-673410.1109/JEDS.2021.3123978https://doaj.org/article/f06ea28a616943c38fa53f2f9bcfa7c32021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9593930/https://doaj.org/toc/2168-6734The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultra-high Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimization to minimize the gate leakage current towards low-power MCU applications. Based on the 55 nm node, it has been found both theoretically and experimentally that the leakage level has been significantly reduced at different temperature in n-FET, p-FET, data flip-flop (DFF) and inverter (INV). Upon MCU testing under active, sleep and deep sleep modes, obvious decrease in the power consumption is also achieved, providing a promising optimization approach towards a better balance between the speed and power in modern MCU technology.Zijian ZhaoYao ZhouHao ZhuQingqing SunDavid Wei ZhangIEEEarticleMCUgate oxidestatic power consumptiongate leakageElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Journal of the Electron Devices Society, Vol 9, Pp 1055-1059 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	MCU gate oxide static power consumption gate leakage Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	MCU gate oxide static power consumption gate leakage Electrical engineering. Electronics. Nuclear engineering TK1-9971 Zijian Zhao Yao Zhou Hao Zhu Qingqing Sun David Wei Zhang Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications
description	The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultra-high Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimization to minimize the gate leakage current towards low-power MCU applications. Based on the 55 nm node, it has been found both theoretically and experimentally that the leakage level has been significantly reduced at different temperature in n-FET, p-FET, data flip-flop (DFF) and inverter (INV). Upon MCU testing under active, sleep and deep sleep modes, obvious decrease in the power consumption is also achieved, providing a promising optimization approach towards a better balance between the speed and power in modern MCU technology.
format	article
author	Zijian Zhao Yao Zhou Hao Zhu Qingqing Sun David Wei Zhang
author_facet	Zijian Zhao Yao Zhou Hao Zhu Qingqing Sun David Wei Zhang
author_sort	Zijian Zhao
title	Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications
title_short	Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications
title_full	Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications
title_fullStr	Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications
title_full_unstemmed	Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications
title_sort	gate oxide and implantation process co-optimization for low-power mcu applications
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/f06ea28a616943c38fa53f2f9bcfa7c3
work_keys_str_mv	AT zijianzhao gateoxideandimplantationprocesscooptimizationforlowpowermcuapplications AT yaozhou gateoxideandimplantationprocesscooptimizationforlowpowermcuapplications AT haozhu gateoxideandimplantationprocesscooptimizationforlowpowermcuapplications AT qingqingsun gateoxideandimplantationprocesscooptimizationforlowpowermcuapplications AT davidweizhang gateoxideandimplantationprocesscooptimizationforlowpowermcuapplications
_version_	1718425259408883712

Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

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