1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering

This paper extends the 1-D systolic array approach with a method of systematic linear design of systolic algorithms. Past methods for mapping the Least-Mean-Square (LMS) Adaptive Finite-Impulse-Response (FIR) filter onto parallel and pipelined architectures either introduce delays in the coefficient...

Descripción completa

Guardado en:

Detalles Bibliográficos
Autores principales:	Ali H. Mahdi, Bakir A. R. Al-Hashemy, Riyadh A.H. AL-Helali
Formato:	article
Lenguaje:	EN
Publicado:	Al-Khwarizmi College of Engineering – University of Baghdad 2010
Materias:	Adaptive signal processing; LMS algorithm; VLSI signal processing. Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040
Acceso en línea:	https://doaj.org/article/f2aab48085e3412099eb31a4975a842b
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

id	oai:doaj.org-article:f2aab48085e3412099eb31a4975a842b
record_format	dspace
spelling	oai:doaj.org-article:f2aab48085e3412099eb31a4975a842b2021-12-02T06:41:03Z1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering1818-1171https://doaj.org/article/f2aab48085e3412099eb31a4975a842b2010-01-01T00:00:00Zhttp://www.iasj.net/iasj?func=fulltext&aId=2249https://doaj.org/toc/1818-1171This paper extends the 1-D systolic array approach with a method of systematic linear design of systolic algorithms. Past methods for mapping the Least-Mean-Square (LMS) Adaptive Finite-Impulse-Response (FIR) filter onto parallel and pipelined architectures either introduce delays in the coefficients updates or have excessive hardware requirements. In this article, we describe an efficient 1-D systolic array for the LMS adaptive FIR filter that produces the same output and error signals as produced by the standard LMS adaptive filter architecture with single assignment form of processor functions.<br />The proposed systolic architectures that are designed operate on a block-by-block basis and makes use of the flexibility in the design, which takes the inner product step (convolution sum) of the tap weight vector and the tap input vector in the design consideration. It enables us to extract more than one algorithm for the same problem. The input and output data flow sequentially and continuously into and out of the systolic arrays at the system clock rates, during each clock period, processing element of the same type operates in parallel. The most computationally demanding among them performs only two consecutive multiplications and two additions/subtractions per clock period, thereby allowing a very high throughput and very fast block signal processing to be achieved at the expense of a delay of L samples between the input and output and 100% utilization, L being the block size.Ali H. MahdiBakir A. R. Al-HashemyRiyadh A.H. AL-HelaliAl-Khwarizmi College of Engineering – University of BaghdadarticleAdaptive signal processing; LMS algorithm; VLSI signal processing.Chemical engineeringTP155-156Engineering (General). Civil engineering (General)TA1-2040ENAl-Khawarizmi Engineering Journal, Vol 6, Iss 1, Pp 88-100 (2010)
institution	DOAJ
collection	DOAJ
language	EN
topic	Adaptive signal processing; LMS algorithm; VLSI signal processing. Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040
spellingShingle	Adaptive signal processing; LMS algorithm; VLSI signal processing. Chemical engineering TP155-156 Engineering (General). Civil engineering (General) TA1-2040 Ali H. Mahdi Bakir A. R. Al-Hashemy Riyadh A.H. AL-Helali 1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering
description	This paper extends the 1-D systolic array approach with a method of systematic linear design of systolic algorithms. Past methods for mapping the Least-Mean-Square (LMS) Adaptive Finite-Impulse-Response (FIR) filter onto parallel and pipelined architectures either introduce delays in the coefficients updates or have excessive hardware requirements. In this article, we describe an efficient 1-D systolic array for the LMS adaptive FIR filter that produces the same output and error signals as produced by the standard LMS adaptive filter architecture with single assignment form of processor functions.<br />The proposed systolic architectures that are designed operate on a block-by-block basis and makes use of the flexibility in the design, which takes the inner product step (convolution sum) of the tap weight vector and the tap input vector in the design consideration. It enables us to extract more than one algorithm for the same problem. The input and output data flow sequentially and continuously into and out of the systolic arrays at the system clock rates, during each clock period, processing element of the same type operates in parallel. The most computationally demanding among them performs only two consecutive multiplications and two additions/subtractions per clock period, thereby allowing a very high throughput and very fast block signal processing to be achieved at the expense of a delay of L samples between the input and output and 100% utilization, L being the block size.
format	article
author	Ali H. Mahdi Bakir A. R. Al-Hashemy Riyadh A.H. AL-Helali
author_facet	Ali H. Mahdi Bakir A. R. Al-Hashemy Riyadh A.H. AL-Helali
author_sort	Ali H. Mahdi
title	1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering
title_short	1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering
title_full	1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering
title_fullStr	1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering
title_full_unstemmed	1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering
title_sort	1-d systolic arrays design of lms adaptive (fir) digital filtering
publisher	Al-Khwarizmi College of Engineering – University of Baghdad
publishDate	2010
url	https://doaj.org/article/f2aab48085e3412099eb31a4975a842b
work_keys_str_mv	AT alihmahdi 1dsystolicarraysdesignoflmsadaptivefirdigitalfiltering AT bakiraralhashemy 1dsystolicarraysdesignoflmsadaptivefirdigitalfiltering AT riyadhahalhelali 1dsystolicarraysdesignoflmsadaptivefirdigitalfiltering
_version_	1718399789124550656

1-D Systolic Arrays Design of LMS Adaptive (FIR) Digital Filtering

Ejemplares similares