All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

Abstract Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital...

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Autores principales:	Lanhua Xia, Jifei Tang
Formato:	article
Lenguaje:	EN
Publicado:	Wiley 2021
Materias:	Computer engineering. Computer hardware TK7885-7895
Acceso en línea:	https://doaj.org/article/f4a029022d09420b8f6679a40282f41d
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spelling	oai:doaj.org-article:f4a029022d09420b8f6679a40282f41d2021-11-06T03:20:47ZAll‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops1751-85981751-858X10.1049/cds2.12000https://doaj.org/article/f4a029022d09420b8f6679a40282f41d2021-01-01T00:00:00Zhttps://doi.org/10.1049/cds2.12000https://doaj.org/toc/1751-858Xhttps://doaj.org/toc/1751-8598Abstract Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.Lanhua XiaJifei TangWileyarticleComputer engineering. Computer hardwareTK7885-7895ENIET Circuits, Devices and Systems, Vol 15, Iss 1, Pp 1-10 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Computer engineering. Computer hardware TK7885-7895
spellingShingle	Computer engineering. Computer hardware TK7885-7895 Lanhua Xia Jifei Tang All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
description	Abstract Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.
format	article
author	Lanhua Xia Jifei Tang
author_facet	Lanhua Xia Jifei Tang
author_sort	Lanhua Xia
title	All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
title_short	All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
title_full	All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
title_fullStr	All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
title_full_unstemmed	All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
title_sort	all‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
publisher	Wiley
publishDate	2021
url	https://doaj.org/article/f4a029022d09420b8f6679a40282f41d
work_keys_str_mv	AT lanhuaxia alldigitalbuiltinselftestschemeforchargepumpphaselockedloops AT jifeitang alldigitalbuiltinselftestschemeforchargepumpphaselockedloops
_version_	1718443954653888512

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

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