All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

Abstract Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital...

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Autores principales: Lanhua Xia, Jifei Tang
Formato: article
Lenguaje:EN
Publicado: Wiley 2021
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Acceso en línea:https://doaj.org/article/f4a029022d09420b8f6679a40282f41d
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