Exploring Cortex-M Microarchitectural Side Channel Information Leakage

The growing Internet of Things (IoT) market demands side-channel attack resistant, efficient, cryptographic implementations. Such implementations, however, are microarchitecture-specific, and cannot be implemented without an in-depth structural knowledge of the CPU and memory information leakage pat...

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Autores principales:	Alessandro Barenghi, Luca Breveglieri, Niccolo Izzo, Gerardo Pelosi
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	Computer security correlation power analysis embedded systems security microarchitectural reverse engineering side channel attack countermeasures Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/fee43eca6be34d29960fc9fe0bfc104f
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spelling	oai:doaj.org-article:fee43eca6be34d29960fc9fe0bfc104f2021-12-02T00:00:14ZExploring Cortex-M Microarchitectural Side Channel Information Leakage2169-353610.1109/ACCESS.2021.3124761https://doaj.org/article/fee43eca6be34d29960fc9fe0bfc104f2021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9598930/https://doaj.org/toc/2169-3536The growing Internet of Things (IoT) market demands side-channel attack resistant, efficient, cryptographic implementations. Such implementations, however, are microarchitecture-specific, and cannot be implemented without an in-depth structural knowledge of the CPU and memory information leakage patterns; a description of such information leakages is presently not disclosed by any processor design company. In this work we propose the first Instruction Set Architecture (ISA) level framework for microarchitectural leakage characterization. Our framework allows to extract a microarchitectural leakage profile from a superscalar in-order processor; we infer detailed pipeline characteristics through the observation of instruction execution timings, and provide an identification of the datapath registers via a side-channel measuring setup. The extracted model can serve as a foundation for building solid countermeasures against side-channel attacks on software cryptographic implementations. We validate the extracted models on the ARM Cortex-M4 and ARM Cortex-M7 CPUs, two of the most widespread ARM microcontroller cores. Finally, as a further validation of the effectiveness of our derived model, we mount a successful attack on unprotected AES implementations for each of the examined platforms.Alessandro BarenghiLuca BreveglieriNiccolo IzzoGerardo PelosiIEEEarticleComputer securitycorrelation power analysisembedded systems securitymicroarchitectural reverse engineeringside channel attack countermeasuresElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Access, Vol 9, Pp 156507-156527 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Computer security correlation power analysis embedded systems security microarchitectural reverse engineering side channel attack countermeasures Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	Computer security correlation power analysis embedded systems security microarchitectural reverse engineering side channel attack countermeasures Electrical engineering. Electronics. Nuclear engineering TK1-9971 Alessandro Barenghi Luca Breveglieri Niccolo Izzo Gerardo Pelosi Exploring Cortex-M Microarchitectural Side Channel Information Leakage
description	The growing Internet of Things (IoT) market demands side-channel attack resistant, efficient, cryptographic implementations. Such implementations, however, are microarchitecture-specific, and cannot be implemented without an in-depth structural knowledge of the CPU and memory information leakage patterns; a description of such information leakages is presently not disclosed by any processor design company. In this work we propose the first Instruction Set Architecture (ISA) level framework for microarchitectural leakage characterization. Our framework allows to extract a microarchitectural leakage profile from a superscalar in-order processor; we infer detailed pipeline characteristics through the observation of instruction execution timings, and provide an identification of the datapath registers via a side-channel measuring setup. The extracted model can serve as a foundation for building solid countermeasures against side-channel attacks on software cryptographic implementations. We validate the extracted models on the ARM Cortex-M4 and ARM Cortex-M7 CPUs, two of the most widespread ARM microcontroller cores. Finally, as a further validation of the effectiveness of our derived model, we mount a successful attack on unprotected AES implementations for each of the examined platforms.
format	article
author	Alessandro Barenghi Luca Breveglieri Niccolo Izzo Gerardo Pelosi
author_facet	Alessandro Barenghi Luca Breveglieri Niccolo Izzo Gerardo Pelosi
author_sort	Alessandro Barenghi
title	Exploring Cortex-M Microarchitectural Side Channel Information Leakage
title_short	Exploring Cortex-M Microarchitectural Side Channel Information Leakage
title_full	Exploring Cortex-M Microarchitectural Side Channel Information Leakage
title_fullStr	Exploring Cortex-M Microarchitectural Side Channel Information Leakage
title_full_unstemmed	Exploring Cortex-M Microarchitectural Side Channel Information Leakage
title_sort	exploring cortex-m microarchitectural side channel information leakage
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/fee43eca6be34d29960fc9fe0bfc104f
work_keys_str_mv	AT alessandrobarenghi exploringcortexmmicroarchitecturalsidechannelinformationleakage AT lucabreveglieri exploringcortexmmicroarchitecturalsidechannelinformationleakage AT niccoloizzo exploringcortexmmicroarchitecturalsidechannelinformationleakage AT gerardopelosi exploringcortexmmicroarchitecturalsidechannelinformationleakage
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Exploring Cortex-M Microarchitectural Side Channel Information Leakage

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