Four stage pipeline quaternary processor
ABSTRACT The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, dom...
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| Autores principales: | , , , |
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| Lenguaje: | English |
| Publicado: |
Universidad de Tarapacá.
2020
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| Materias: | |
| Acceso en línea: | http://www.scielo.cl/scielo.php?script=sci_arttext&pid=S0718-33052020000300540 |
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| Sumario: | ABSTRACT The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, domain D: {0, 1, 2, 3} reduces the number of connections due to the fact that, approximately, 70% of the circuit area is being used for interconnections and pads. This work proposes the design of a four stages pipelined quaternary processor (eCPU) with sixteen instructions and the handling of hazards utilizing hybrid (static and dynamic) techniques with the scope to demonstrate the correct functionality with respect to the design specification, based on a universal set of quaternary logic gates already proposed in the literature. The eCPU has been designed via hardware description in Quartus® environment written in VHSIC Hardware Description Language (VHDL) and simulations performed in ModelSim®, demonstrating the correct behavior with respect to the specifications. The simulations are performed by executing several programs written in the chosen quaternary assembly language with the support of a two phase's compiler written in Java to generate quaternary machine code. |
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