Four stage pipeline quaternary processor

ABSTRACT The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, dom...

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Autores principales:	Gouveia,Tiago, Oliveira,Wellington, Romero Romero,Milton Ernesto, Mazina Martins,Evandro
Lenguaje:	English
Publicado:	Universidad de Tarapacá. 2020
Materias:	Control processing unit multi valued-logic quaternary compiler
Acceso en línea:	http://www.scielo.cl/scielo.php?script=sci_arttext&pid=S0718-33052020000300540
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spelling	oai:scielo:S0718-330520200003005402020-11-03Four stage pipeline quaternary processorGouveia,TiagoOliveira,WellingtonRomero Romero,Milton ErnestoMazina Martins,Evandro Control processing unit multi valued-logic quaternary compiler ABSTRACT The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, domain D: {0, 1, 2, 3} reduces the number of connections due to the fact that, approximately, 70% of the circuit area is being used for interconnections and pads. This work proposes the design of a four stages pipelined quaternary processor (eCPU) with sixteen instructions and the handling of hazards utilizing hybrid (static and dynamic) techniques with the scope to demonstrate the correct functionality with respect to the design specification, based on a universal set of quaternary logic gates already proposed in the literature. The eCPU has been designed via hardware description in Quartus® environment written in VHSIC Hardware Description Language (VHDL) and simulations performed in ModelSim®, demonstrating the correct behavior with respect to the specifications. The simulations are performed by executing several programs written in the chosen quaternary assembly language with the support of a two phase's compiler written in Java to generate quaternary machine code.info:eu-repo/semantics/openAccessUniversidad de Tarapacá.Ingeniare. Revista chilena de ingeniería v.28 n.3 20202020-09-01text/htmlhttp://www.scielo.cl/scielo.php?script=sci_arttext&pid=S0718-33052020000300540en10.4067/S0718-33052020000300540
institution	Scielo Chile
collection	Scielo Chile
language	English
topic	Control processing unit multi valued-logic quaternary compiler
spellingShingle	Control processing unit multi valued-logic quaternary compiler Gouveia,Tiago Oliveira,Wellington Romero Romero,Milton Ernesto Mazina Martins,Evandro Four stage pipeline quaternary processor
description	ABSTRACT The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, domain D: {0, 1, 2, 3} reduces the number of connections due to the fact that, approximately, 70% of the circuit area is being used for interconnections and pads. This work proposes the design of a four stages pipelined quaternary processor (eCPU) with sixteen instructions and the handling of hazards utilizing hybrid (static and dynamic) techniques with the scope to demonstrate the correct functionality with respect to the design specification, based on a universal set of quaternary logic gates already proposed in the literature. The eCPU has been designed via hardware description in Quartus® environment written in VHSIC Hardware Description Language (VHDL) and simulations performed in ModelSim®, demonstrating the correct behavior with respect to the specifications. The simulations are performed by executing several programs written in the chosen quaternary assembly language with the support of a two phase's compiler written in Java to generate quaternary machine code.
author	Gouveia,Tiago Oliveira,Wellington Romero Romero,Milton Ernesto Mazina Martins,Evandro
author_facet	Gouveia,Tiago Oliveira,Wellington Romero Romero,Milton Ernesto Mazina Martins,Evandro
author_sort	Gouveia,Tiago
title	Four stage pipeline quaternary processor
title_short	Four stage pipeline quaternary processor
title_full	Four stage pipeline quaternary processor
title_fullStr	Four stage pipeline quaternary processor
title_full_unstemmed	Four stage pipeline quaternary processor
title_sort	four stage pipeline quaternary processor
publisher	Universidad de Tarapacá.
publishDate	2020
url	http://www.scielo.cl/scielo.php?script=sci_arttext&pid=S0718-33052020000300540
work_keys_str_mv	AT gouveiatiago fourstagepipelinequaternaryprocessor AT oliveirawellington fourstagepipelinequaternaryprocessor AT romeroromeromiltonernesto fourstagepipelinequaternaryprocessor AT mazinamartinsevandro fourstagepipelinequaternaryprocessor
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Four stage pipeline quaternary processor

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