Superjunction Power Transistors With Interface Charges: A Case Study for GaN

Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performanc...

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Autores principales:	Yunwei Ma, Ming Xiao, Ruizhe Zhang, Han Wang, Yuhao Zhang
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2020
Materias:	Power electronics power semiconductor devices superjunction interface charges interface impurities gallium nitride Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/00582700c8e245ffabfc1b5cce9d4da1
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spelling	oai:doaj.org-article:00582700c8e245ffabfc1b5cce9d4da12021-11-19T00:01:17ZSuperjunction Power Transistors With Interface Charges: A Case Study for GaN2168-673410.1109/JEDS.2019.2959713https://doaj.org/article/00582700c8e245ffabfc1b5cce9d4da12020-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/8932530/https://doaj.org/toc/2168-6734Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges for the first time. In our model, two approaches are proposed to compensate interface charges, by the modulation of the SJ doping or the SJ geometry. Based on our model, an analytical study is conducted for GaN SJ transistors, revealing the design windows and optimal values of doping concentration and pillar width as a function of interface charge density. Finally, TCAD simulation is performed for vertical GaN SJ transistors, which validated our analytical model. Our results show that, with optimal designs, interface charges would only induce small degradation in the performance of GaN SJ devices. However, with the increased interface charge density, the design windows for pillar width and doping concentration become increasingly narrow and the upper limit in the pillar width window reduces quickly. When the interface charge density exceeds <inline-formula> <tex-math notation="LaTeX">$\sim 3\times 10^{12}$ </tex-math></inline-formula> cm<sup>−2</sup>, the design window of pillar width completely falls into the sub-micron range, indicating significant difficulties in fabrication. Vertical GaN SJ transistors with interface charges retain great advantages over conventional GaN power transistors, but have narrower design windows and require different design rules compared to ideal GaN SJ devices.Yunwei MaMing XiaoRuizhe ZhangHan WangYuhao ZhangIEEEarticlePower electronicspower semiconductor devicessuperjunctioninterface chargesinterface impuritiesgallium nitrideElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Journal of the Electron Devices Society, Vol 8, Pp 42-48 (2020)
institution	DOAJ
collection	DOAJ
language	EN
topic	Power electronics power semiconductor devices superjunction interface charges interface impurities gallium nitride Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	Power electronics power semiconductor devices superjunction interface charges interface impurities gallium nitride Electrical engineering. Electronics. Nuclear engineering TK1-9971 Yunwei Ma Ming Xiao Ruizhe Zhang Han Wang Yuhao Zhang Superjunction Power Transistors With Interface Charges: A Case Study for GaN
description	Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges for the first time. In our model, two approaches are proposed to compensate interface charges, by the modulation of the SJ doping or the SJ geometry. Based on our model, an analytical study is conducted for GaN SJ transistors, revealing the design windows and optimal values of doping concentration and pillar width as a function of interface charge density. Finally, TCAD simulation is performed for vertical GaN SJ transistors, which validated our analytical model. Our results show that, with optimal designs, interface charges would only induce small degradation in the performance of GaN SJ devices. However, with the increased interface charge density, the design windows for pillar width and doping concentration become increasingly narrow and the upper limit in the pillar width window reduces quickly. When the interface charge density exceeds <inline-formula> <tex-math notation="LaTeX">$\sim 3\times 10^{12}$ </tex-math></inline-formula> cm<sup>−2</sup>, the design window of pillar width completely falls into the sub-micron range, indicating significant difficulties in fabrication. Vertical GaN SJ transistors with interface charges retain great advantages over conventional GaN power transistors, but have narrower design windows and require different design rules compared to ideal GaN SJ devices.
format	article
author	Yunwei Ma Ming Xiao Ruizhe Zhang Han Wang Yuhao Zhang
author_facet	Yunwei Ma Ming Xiao Ruizhe Zhang Han Wang Yuhao Zhang
author_sort	Yunwei Ma
title	Superjunction Power Transistors With Interface Charges: A Case Study for GaN
title_short	Superjunction Power Transistors With Interface Charges: A Case Study for GaN
title_full	Superjunction Power Transistors With Interface Charges: A Case Study for GaN
title_fullStr	Superjunction Power Transistors With Interface Charges: A Case Study for GaN
title_full_unstemmed	Superjunction Power Transistors With Interface Charges: A Case Study for GaN
title_sort	superjunction power transistors with interface charges: a case study for gan
publisher	IEEE
publishDate	2020
url	https://doaj.org/article/00582700c8e245ffabfc1b5cce9d4da1
work_keys_str_mv	AT yunweima superjunctionpowertransistorswithinterfacechargesacasestudyforgan AT mingxiao superjunctionpowertransistorswithinterfacechargesacasestudyforgan AT ruizhezhang superjunctionpowertransistorswithinterfacechargesacasestudyforgan AT hanwang superjunctionpowertransistorswithinterfacechargesacasestudyforgan AT yuhaozhang superjunctionpowertransistorswithinterfacechargesacasestudyforgan
_version_	1718420647595474944

Superjunction Power Transistors With Interface Charges: A Case Study for GaN

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