Templated dewetting of single-crystal sub-millimeter-long nanowires and on-chip silicon circuits
Fabricating defect-free micro- and nano-circuits over large scales with controlled interconnections remains a challenge. Here, Bollani et al. show a dewetting strategy for engineering arrays of parallel Si-based nanowires up to 0.75 mm and complex interconnected circuits of monocrystalline Si on a c...
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| Autores principales: | , , , , , , , , , , , , , , , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
Nature Portfolio
2019
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/21de977ef4894f20829d7bd10b3c7fe3 |
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