Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize...

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Autores principales:	Jan Richter-Brockmann, Ming-Shing Chen, Santosh Ghosh, Tim Güneysu
Formato:	article
Lenguaje:	EN
Publicado:	Ruhr-Universität Bochum 2021
Materias:	BIKE QC-MDPC PQC Reconfigurable Devices FPGA Computer engineering. Computer hardware TK7885-7895 Information technology T58.5-58.64
Acceso en línea:	https://doaj.org/article/2e316b33aa4143dcb95734bcd0b41ecd
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spelling	oai:doaj.org-article:2e316b33aa4143dcb95734bcd0b41ecd2021-11-19T14:36:06ZRacing BIKE: Improved Polynomial Multiplication and Inversion in Hardware10.46586/tches.v2022.i1.557-5882569-2925https://doaj.org/article/2e316b33aa4143dcb95734bcd0b41ecd2021-11-01T00:00:00Zhttps://tches.iacr.org/index.php/TCHES/article/view/9307https://doaj.org/toc/2569-2925 BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize two key arithmetic operations, which are the sparse polynomial multiplication and the polynomial inversion. Our sparse multiplier achieves time-constancy for sparse polynomials of indefinite Hamming weight used in BIKE’s encapsulation. The polynomial inversion is based on the extended Euclidean algorithm, which is unprecedented in current BIKE implementations. Our optimized design results in a 5.5 times faster key generation compared to previous implementations based on Fermat’s little theorem. Besides the arithmetic optimizations, we present a united hardware design of BIKE with shared resources and shared sub-modules among KEM functionalities. On Xilinx Artix-7 FPGAs, our light-weight implementation consumes only 3 777 slices and performs a key generation, encapsulation, and decapsulation in 3 797 μs, 443 μs, and 6 896 μs, respectively. Our high-speed design requires 7 332 slices and performs the three KEM operations in 1 672 μs, 132 μs, and 1 892 μs, respectively. Jan Richter-BrockmannMing-Shing ChenSantosh GhoshTim GüneysuRuhr-Universität BochumarticleBIKEQC-MDPCPQCReconfigurable DevicesFPGAComputer engineering. Computer hardwareTK7885-7895Information technologyT58.5-58.64ENTransactions on Cryptographic Hardware and Embedded Systems, Vol 2022, Iss 1 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	BIKE QC-MDPC PQC Reconfigurable Devices FPGA Computer engineering. Computer hardware TK7885-7895 Information technology T58.5-58.64
spellingShingle	BIKE QC-MDPC PQC Reconfigurable Devices FPGA Computer engineering. Computer hardware TK7885-7895 Information technology T58.5-58.64 Jan Richter-Brockmann Ming-Shing Chen Santosh Ghosh Tim Güneysu Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware
description	BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize two key arithmetic operations, which are the sparse polynomial multiplication and the polynomial inversion. Our sparse multiplier achieves time-constancy for sparse polynomials of indefinite Hamming weight used in BIKE’s encapsulation. The polynomial inversion is based on the extended Euclidean algorithm, which is unprecedented in current BIKE implementations. Our optimized design results in a 5.5 times faster key generation compared to previous implementations based on Fermat’s little theorem. Besides the arithmetic optimizations, we present a united hardware design of BIKE with shared resources and shared sub-modules among KEM functionalities. On Xilinx Artix-7 FPGAs, our light-weight implementation consumes only 3 777 slices and performs a key generation, encapsulation, and decapsulation in 3 797 μs, 443 μs, and 6 896 μs, respectively. Our high-speed design requires 7 332 slices and performs the three KEM operations in 1 672 μs, 132 μs, and 1 892 μs, respectively.
format	article
author	Jan Richter-Brockmann Ming-Shing Chen Santosh Ghosh Tim Güneysu
author_facet	Jan Richter-Brockmann Ming-Shing Chen Santosh Ghosh Tim Güneysu
author_sort	Jan Richter-Brockmann
title	Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware
title_short	Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware
title_full	Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware
title_fullStr	Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware
title_full_unstemmed	Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware
title_sort	racing bike: improved polynomial multiplication and inversion in hardware
publisher	Ruhr-Universität Bochum
publishDate	2021
url	https://doaj.org/article/2e316b33aa4143dcb95734bcd0b41ecd
work_keys_str_mv	AT janrichterbrockmann racingbikeimprovedpolynomialmultiplicationandinversioninhardware AT mingshingchen racingbikeimprovedpolynomialmultiplicationandinversioninhardware AT santoshghosh racingbikeimprovedpolynomialmultiplicationandinversioninhardware AT timguneysu racingbikeimprovedpolynomialmultiplicationandinversioninhardware
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Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

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