Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware
BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize...
Saved in:
Main Authors: | Jan Richter-Brockmann, Ming-Shing Chen, Santosh Ghosh, Tim Güneysu |
---|---|
Format: | article |
Language: | EN |
Published: |
Ruhr-Universität Bochum
2021
|
Subjects: | |
Online Access: | https://doaj.org/article/2e316b33aa4143dcb95734bcd0b41ecd |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium
by: Cankun Zhao, et al.
Published: (2021) -
A Constant-time AVX2 Implementation of a Variant of ROLLO
by: Tung Chou, et al.
Published: (2021) -
Neon NTT: Faster Dilithium, Kyber, and Saber on Cortex-A72 and Apple M1
by: Hanno Becker, et al.
Published: (2021) -
Automated Generation of Masked Hardware
by: David Knichel, et al.
Published: (2021) -
VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs
by: Brian Udugama, et al.
Published: (2021)