Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device

For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and length of diffusion effect. Based on the oxygen diffu...

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Autores principales:	Ying-Fei Wang, Qing-Chun Zhang, Ping Li, Xiao-Jing Su, Li-Song Dong, Rui Chen, Li-Bin Zhang, Tian-Yang Gai, Ya-Juan Su, Ya-Yi Wei, Tian Chun Ye
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	Layout proximity effects high-k HfO₂ stress memorization technique Al diffusion Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/3269a09e61a045ebb74841b3612bc1ff
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

id	oai:doaj.org-article:3269a09e61a045ebb74841b3612bc1ff
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spelling	oai:doaj.org-article:3269a09e61a045ebb74841b3612bc1ff2021-11-19T00:01:46ZUnderstanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device2168-673410.1109/JEDS.2020.3032957https://doaj.org/article/3269a09e61a045ebb74841b3612bc1ff2021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9235562/https://doaj.org/toc/2168-6734For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and length of diffusion effect. Based on the oxygen diffusion mechanism analysis of layout proximity effects in high-k/Metal gate NMOS device, an optimized process is proposed to suppress the layout dependency. The experiment result indicates that modified low temperature stress memorization technique process can suppress layout dependency efficiently without performance degradation of the devices.Ying-Fei WangQing-Chun ZhangPing LiXiao-Jing SuLi-Song DongRui ChenLi-Bin ZhangTian-Yang GaiYa-Juan SuYa-Yi WeiTian Chun YeIEEEarticleLayout proximity effectshigh-k HfO₂stress memorization techniqueAl diffusionElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Journal of the Electron Devices Society, Vol 9, Pp 6-9 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Layout proximity effects high-k HfO₂ stress memorization technique Al diffusion Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	Layout proximity effects high-k HfO₂ stress memorization technique Al diffusion Electrical engineering. Electronics. Nuclear engineering TK1-9971 Ying-Fei Wang Qing-Chun Zhang Ping Li Xiao-Jing Su Li-Song Dong Rui Chen Li-Bin Zhang Tian-Yang Gai Ya-Juan Su Ya-Yi Wei Tian Chun Ye Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
description	For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and length of diffusion effect. Based on the oxygen diffusion mechanism analysis of layout proximity effects in high-k/Metal gate NMOS device, an optimized process is proposed to suppress the layout dependency. The experiment result indicates that modified low temperature stress memorization technique process can suppress layout dependency efficiently without performance degradation of the devices.
format	article
author	Ying-Fei Wang Qing-Chun Zhang Ping Li Xiao-Jing Su Li-Song Dong Rui Chen Li-Bin Zhang Tian-Yang Gai Ya-Juan Su Ya-Yi Wei Tian Chun Ye
author_facet	Ying-Fei Wang Qing-Chun Zhang Ping Li Xiao-Jing Su Li-Song Dong Rui Chen Li-Bin Zhang Tian-Yang Gai Ya-Juan Su Ya-Yi Wei Tian Chun Ye
author_sort	Ying-Fei Wang
title	Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
title_short	Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
title_full	Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
title_fullStr	Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
title_full_unstemmed	Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
title_sort	understanding and mitigating stress memorization technique of induced layout dependencies for nmos hkmg device
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/3269a09e61a045ebb74841b3612bc1ff
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_version_	1718420661082259456

Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device

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