Effects of temperature conditions on fracture toughness of single crystal silicon wafer
This paper provides effects of furnace temperature conditions on the fracture toughness value of cleavage plane {110} on a single crystal silicon wafer. The fracture toughness KIC was measured using the controlled surface flaw (CSF) method under an assumption to develop a thin crack introduced by a...
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| Autores principales: | , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
The Japan Society of Mechanical Engineers
2019
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/3a8dbfd35df649228ebfa1e73d67c99d |
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| Sumario: | This paper provides effects of furnace temperature conditions on the fracture toughness value of cleavage plane {110} on a single crystal silicon wafer. The fracture toughness KIC was measured using the controlled surface flaw (CSF) method under an assumption to develop a thin crack introduced by a Vickers indenter. A system for evaluating four-point bending fracture strength under high temperature conditions was designed and constructed. This system can provide fracture strength under high temperature conditions for small plate specimens cut from the single crystal silicon wafer. CSF method needs to remove the surface layer, since residual stresses may be formed around the indentation mark and crack introduced by the indenter. Ion shower, can control micrometer order the removal surface layer, was applied for this analysis. An appropriate removal amount of the surface layer was confirmed based on effects of removal amount of surface on the fracture toughness in a room temperature condition. This result was applied for evaluations for the fracture toughness under various temperature conditions. Effects of furnace temperature condition on the fracture toughness and the fracture patterns were experimentally clarified in ranged over from room temperature to 600 °C. Above effects were compared with a result obtained from specimens without the removal process of the surface. Fracture's behaviors on the cleavage plane {110} of the single crystal silicon wafer in the high temperature range were discussed based on these experimental results. |
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