Power optimized variation aware dual-threshold SRAM cell design technique

Aminul Islam1, Mohd Hasan21Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India; 2Department of Electronics Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh, IndiaAbstract: Bulk complementary metal-oxide semiconductor (...

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Autores principales:	Aminul Islam, Mohd Hasan
Formato:	article
Lenguaje:	EN
Publicado:	Dove Medical Press 2011
Materias:	Medical technology R855-855.5 Chemical technology TP1-1185
Acceso en línea:	https://doaj.org/article/51f72d6328774c3aa2acae6eed7ef7e7
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spelling	oai:doaj.org-article:51f72d6328774c3aa2acae6eed7ef7e72021-12-02T08:24:25ZPower optimized variation aware dual-threshold SRAM cell design technique1177-8903https://doaj.org/article/51f72d6328774c3aa2acae6eed7ef7e72011-02-01T00:00:00Zhttp://www.dovepress.com/power-optimized-variation-aware-dual-threshold-sram-cell-design-techni-a6285https://doaj.org/toc/1177-8903Aminul Islam1, Mohd Hasan21Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India; 2Department of Electronics Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh, IndiaAbstract: Bulk complementary metal-oxide semiconductor (CMOS) technology is facing enormous challenges at channel lengths below 45 nm, such as gate tunneling, device mismatch, random dopant fluctuations, and mobility degradation. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube-based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology. In this paper, we propose a low-power variation-immune dual-threshold voltage carbon nanotube field effect transistor (CNFET)-based seven-transistor (7T) static random access memory (SRAM) cell. The proposed CNFET-based 7T SRAM cell offers ~1.2&times; improvement in standby power, ~1.3&times; improvement in read delay, and ~1.1&times; improvement in write delay. It offers narrower spread in write access time (1.4&times; at optimum energy point [OEP] and 1.2&times; at 1 V). It features 56.3% improvement in static noise margin and 40% improvement in read static noise margin. All the simulation measurements are taken at proposed OEP decided by the optimum results obtained after extensive simulation on HSPICE (high-performance simulation program with integrated circuit emphasis) environment.Keywords: carbon nanotube field effect transistor (CNFET), chirality vector, random dopant fluctuation (RDF), SNM Aminul IslamMohd HasanDove Medical PressarticleMedical technologyR855-855.5Chemical technologyTP1-1185ENNanotechnology, Science and Applications, Vol 2011, Iss default, Pp 25-33 (2011)
institution	DOAJ
collection	DOAJ
language	EN
topic	Medical technology R855-855.5 Chemical technology TP1-1185
spellingShingle	Medical technology R855-855.5 Chemical technology TP1-1185 Aminul Islam Mohd Hasan Power optimized variation aware dual-threshold SRAM cell design technique
description	Aminul Islam1, Mohd Hasan21Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India; 2Department of Electronics Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh, IndiaAbstract: Bulk complementary metal-oxide semiconductor (CMOS) technology is facing enormous challenges at channel lengths below 45 nm, such as gate tunneling, device mismatch, random dopant fluctuations, and mobility degradation. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube-based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology. In this paper, we propose a low-power variation-immune dual-threshold voltage carbon nanotube field effect transistor (CNFET)-based seven-transistor (7T) static random access memory (SRAM) cell. The proposed CNFET-based 7T SRAM cell offers ~1.2&times; improvement in standby power, ~1.3&times; improvement in read delay, and ~1.1&times; improvement in write delay. It offers narrower spread in write access time (1.4&times; at optimum energy point [OEP] and 1.2&times; at 1 V). It features 56.3% improvement in static noise margin and 40% improvement in read static noise margin. All the simulation measurements are taken at proposed OEP decided by the optimum results obtained after extensive simulation on HSPICE (high-performance simulation program with integrated circuit emphasis) environment.Keywords: carbon nanotube field effect transistor (CNFET), chirality vector, random dopant fluctuation (RDF), SNM
format	article
author	Aminul Islam Mohd Hasan
author_facet	Aminul Islam Mohd Hasan
author_sort	Aminul Islam
title	Power optimized variation aware dual-threshold SRAM cell design technique
title_short	Power optimized variation aware dual-threshold SRAM cell design technique
title_full	Power optimized variation aware dual-threshold SRAM cell design technique
title_fullStr	Power optimized variation aware dual-threshold SRAM cell design technique
title_full_unstemmed	Power optimized variation aware dual-threshold SRAM cell design technique
title_sort	power optimized variation aware dual-threshold sram cell design technique
publisher	Dove Medical Press
publishDate	2011
url	https://doaj.org/article/51f72d6328774c3aa2acae6eed7ef7e7
work_keys_str_mv	AT aminulislam poweroptimizedvariationawaredualthresholdsramcelldesigntechnique AT mohdhasan poweroptimizedvariationawaredualthresholdsramcelldesigntechnique
_version_	1718398542534410240

Power optimized variation aware dual-threshold SRAM cell design technique

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