Ultrathin Sub-5-nm Hf₁₋<italic>ₓ</italic>Zr<italic>ₓ</italic>O₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate
This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf<sub>1-<italic>x</italic></sub>Zr<italic>x</italic>O2 (HZO). A conventi...
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2021
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oai:doaj.org-article:5ac82faab6e2474280122c96baced3f72021-11-19T00:01:55ZUltrathin Sub-5-nm Hf₁₋<italic>ₓ</italic>Zr<italic>ₓ</italic>O₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate2168-673410.1109/JEDS.2021.3056438https://doaj.org/article/5ac82faab6e2474280122c96baced3f72021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9344700/https://doaj.org/toc/2168-6734This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf<sub>1-<italic>x</italic></sub>Zr<italic>x</italic>O2 (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO<sub>2</sub>) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using a sub-5-nm HZO and seed layer to fabricate a gate-all-around (GAA) nanowire (NW); a FeFET with a metal-ferroelectric–metal-insulator-semiconductor (MFMIS) structure; and a double layer (DL) of the channel. The channel size used in the experiment was approximately <inline-formula> <tex-math notation="LaTeX">$9.6\times16$ </tex-math></inline-formula> nm<sup>2</sup> and the total thickness of the gate stack was 9.2 nm. This thickness is 50.5% less than our previous experiment. The FeFET exhibits a considerably high <inline-formula> <tex-math notation="LaTeX">${I}_{on}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">${I}_{off}$ </tex-math></inline-formula> ratio exceeding 107. The IMG serves as a potential equalizer and the ferroelectric material is arranged in a more symmetrical electric field. This results in a lower subthreshold (sub-<inline-formula> <tex-math notation="LaTeX">${V}_{TH}$ </tex-math></inline-formula>) swing (<inline-formula> <tex-math notation="LaTeX">$S.S._{min}=$ </tex-math></inline-formula> 49.3mV/decade) with a wide range (<inline-formula> <tex-math notation="LaTeX">$10^{3}$ </tex-math></inline-formula>) of drain currentcompared to that without an IMG. The findings indicate that a high-performance GAA FET can be achieved by combining a DL channel, GAA NW, ferroelectric material, and an IMG.Shen-Yang LeeChia-Chin LeeYi-Shan KuoShou-Wei LiTien-Sheng ChaoIEEEarticleStacked channelgate-all-aroundnanowireFeFETPoly-SiMFMISElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Journal of the Electron Devices Society, Vol 9, Pp 236-241 (2021) |
| institution |
DOAJ |
| collection |
DOAJ |
| language |
EN |
| topic |
Stacked channel gate-all-around nanowire FeFET Poly-Si MFMIS Electrical engineering. Electronics. Nuclear engineering TK1-9971 |
| spellingShingle |
Stacked channel gate-all-around nanowire FeFET Poly-Si MFMIS Electrical engineering. Electronics. Nuclear engineering TK1-9971 Shen-Yang Lee Chia-Chin Lee Yi-Shan Kuo Shou-Wei Li Tien-Sheng Chao Ultrathin Sub-5-nm Hf₁₋<italic>ₓ</italic>Zr<italic>ₓ</italic>O₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate |
| description |
This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf<sub>1-<italic>x</italic></sub>Zr<italic>x</italic>O2 (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO<sub>2</sub>) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using a sub-5-nm HZO and seed layer to fabricate a gate-all-around (GAA) nanowire (NW); a FeFET with a metal-ferroelectric–metal-insulator-semiconductor (MFMIS) structure; and a double layer (DL) of the channel. The channel size used in the experiment was approximately <inline-formula> <tex-math notation="LaTeX">$9.6\times16$ </tex-math></inline-formula> nm<sup>2</sup> and the total thickness of the gate stack was 9.2 nm. This thickness is 50.5% less than our previous experiment. The FeFET exhibits a considerably high <inline-formula> <tex-math notation="LaTeX">${I}_{on}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">${I}_{off}$ </tex-math></inline-formula> ratio exceeding 107. The IMG serves as a potential equalizer and the ferroelectric material is arranged in a more symmetrical electric field. This results in a lower subthreshold (sub-<inline-formula> <tex-math notation="LaTeX">${V}_{TH}$ </tex-math></inline-formula>) swing (<inline-formula> <tex-math notation="LaTeX">$S.S._{min}=$ </tex-math></inline-formula> 49.3mV/decade) with a wide range (<inline-formula> <tex-math notation="LaTeX">$10^{3}$ </tex-math></inline-formula>) of drain currentcompared to that without an IMG. The findings indicate that a high-performance GAA FET can be achieved by combining a DL channel, GAA NW, ferroelectric material, and an IMG. |
| format |
article |
| author |
Shen-Yang Lee Chia-Chin Lee Yi-Shan Kuo Shou-Wei Li Tien-Sheng Chao |
| author_facet |
Shen-Yang Lee Chia-Chin Lee Yi-Shan Kuo Shou-Wei Li Tien-Sheng Chao |
| author_sort |
Shen-Yang Lee |
| title |
Ultrathin Sub-5-nm Hf₁₋<italic>ₓ</italic>Zr<italic>ₓ</italic>O₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate |
| title_short |
Ultrathin Sub-5-nm Hf₁₋<italic>ₓ</italic>Zr<italic>ₓ</italic>O₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate |
| title_full |
Ultrathin Sub-5-nm Hf₁₋<italic>ₓ</italic>Zr<italic>ₓ</italic>O₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate |
| title_fullStr |
Ultrathin Sub-5-nm Hf₁₋<italic>ₓ</italic>Zr<italic>ₓ</italic>O₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate |
| title_full_unstemmed |
Ultrathin Sub-5-nm Hf₁₋<italic>ₓ</italic>Zr<italic>ₓ</italic>O₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate |
| title_sort |
ultrathin sub-5-nm hf₁₋<italic>ₓ</italic>zr<italic>ₓ</italic>o₂ for a stacked gate-all-around nanowire ferroelectric fet with internal metal gate |
| publisher |
IEEE |
| publishDate |
2021 |
| url |
https://doaj.org/article/5ac82faab6e2474280122c96baced3f7 |
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