Ratio-based multi-level resistive memory cells

Abstract Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, whic...

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Autores principales:	Miguel Angel Lastras-Montaño, Osvaldo Del Pozo-Zamudio, Lev Glebsky, Meiran Zhao, Huaqiang Wu, Kwang-Ting Cheng
Formato:	article
Lenguaje:	EN
Publicado:	Nature Portfolio 2021
Materias:	Medicine R Science Q
Acceso en línea:	https://doaj.org/article/64d1ad883e3744978f35981114bc5d9a
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spelling	oai:doaj.org-article:64d1ad883e3744978f35981114bc5d9a2021-12-02T14:01:20ZRatio-based multi-level resistive memory cells10.1038/s41598-020-80121-72045-2322https://doaj.org/article/64d1ad883e3744978f35981114bc5d9a2021-01-01T00:00:00Zhttps://doi.org/10.1038/s41598-020-80121-7https://doaj.org/toc/2045-2322Abstract Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to $$x^2$$ x 2 at the best case and $$x^{\sqrt{2}}$$ x 2 at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell’s programming time and programming energy by up 5–10 $$\times$$ × , while achieving the same bit error probability.Miguel Angel Lastras-MontañoOsvaldo Del Pozo-ZamudioLev GlebskyMeiran ZhaoHuaqiang WuKwang-Ting ChengNature PortfolioarticleMedicineRScienceQENScientific Reports, Vol 11, Iss 1, Pp 1-12 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Medicine R Science Q
spellingShingle	Medicine R Science Q Miguel Angel Lastras-Montaño Osvaldo Del Pozo-Zamudio Lev Glebsky Meiran Zhao Huaqiang Wu Kwang-Ting Cheng Ratio-based multi-level resistive memory cells
description	Abstract Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to $$x^2$$ x 2 at the best case and $$x^{\sqrt{2}}$$ x 2 at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell’s programming time and programming energy by up 5–10 $$\times$$ × , while achieving the same bit error probability.
format	article
author	Miguel Angel Lastras-Montaño Osvaldo Del Pozo-Zamudio Lev Glebsky Meiran Zhao Huaqiang Wu Kwang-Ting Cheng
author_facet	Miguel Angel Lastras-Montaño Osvaldo Del Pozo-Zamudio Lev Glebsky Meiran Zhao Huaqiang Wu Kwang-Ting Cheng
author_sort	Miguel Angel Lastras-Montaño
title	Ratio-based multi-level resistive memory cells
title_short	Ratio-based multi-level resistive memory cells
title_full	Ratio-based multi-level resistive memory cells
title_fullStr	Ratio-based multi-level resistive memory cells
title_full_unstemmed	Ratio-based multi-level resistive memory cells
title_sort	ratio-based multi-level resistive memory cells
publisher	Nature Portfolio
publishDate	2021
url	https://doaj.org/article/64d1ad883e3744978f35981114bc5d9a
work_keys_str_mv	AT miguelangellastrasmontano ratiobasedmultilevelresistivememorycells AT osvaldodelpozozamudio ratiobasedmultilevelresistivememorycells AT levglebsky ratiobasedmultilevelresistivememorycells AT meiranzhao ratiobasedmultilevelresistivememorycells AT huaqiangwu ratiobasedmultilevelresistivememorycells AT kwangtingcheng ratiobasedmultilevelresistivememorycells
_version_	1718392203571625984

Ratio-based multi-level resistive memory cells

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