Cita APA (7a ed.)

Min, S., & Cho, W. (2020). CMOS-compatible synaptic transistor gated by chitosan electrolyte-Ta2O5 hybrid electric double layer. Nature Portfolio.

Cita Chicago Style (17a ed.)

Min, Shin-Yi, y Won-Ju Cho. CMOS-compatible Synaptic Transistor Gated by Chitosan Electrolyte-Ta2O5 Hybrid Electric Double Layer. Nature Portfolio, 2020.

Cita MLA (8a ed.)

Min, Shin-Yi, y Won-Ju Cho. CMOS-compatible Synaptic Transistor Gated by Chitosan Electrolyte-Ta2O5 Hybrid Electric Double Layer. Nature Portfolio, 2020.

Precaución: Estas citas no son 100% exactas.