Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (S...

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Autores principales:	Stefan Biereigel, Szymon Kulis, Paulo Moreira, Alexander Kölpin, Paul Leroux, Jeffrey Prinzie
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	All-Digital PLL CDR Single-Event Effects radiation hardening Electronics TK7800-8360
Acceso en línea:	https://doaj.org/article/876fa46e37a041b690ea5a9954a41008
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spelling	oai:doaj.org-article:876fa46e37a041b690ea5a9954a410082021-11-25T17:24:09ZRadiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS10.3390/electronics102227412079-9292https://doaj.org/article/876fa46e37a041b690ea5a9954a410082021-11-01T00:00:00Zhttps://www.mdpi.com/2079-9292/10/22/2741https://doaj.org/toc/2079-9292This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm<sup>2</sup> mg<sup>−1</sup> as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>235</mn></mrow></semantics></math></inline-formula> dB.Stefan BiereigelSzymon KulisPaulo MoreiraAlexander KölpinPaul LerouxJeffrey PrinzieMDPI AGarticleAll-DigitalPLLCDRSingle-Event Effectsradiation hardeningElectronicsTK7800-8360ENElectronics, Vol 10, Iss 2741, p 2741 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	All-Digital PLL CDR Single-Event Effects radiation hardening Electronics TK7800-8360
spellingShingle	All-Digital PLL CDR Single-Event Effects radiation hardening Electronics TK7800-8360 Stefan Biereigel Szymon Kulis Paulo Moreira Alexander Kölpin Paul Leroux Jeffrey Prinzie Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
description	This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm<sup>2</sup> mg<sup>−1</sup> as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>235</mn></mrow></semantics></math></inline-formula> dB.
format	article
author	Stefan Biereigel Szymon Kulis Paulo Moreira Alexander Kölpin Paul Leroux Jeffrey Prinzie
author_facet	Stefan Biereigel Szymon Kulis Paulo Moreira Alexander Kölpin Paul Leroux Jeffrey Prinzie
author_sort	Stefan Biereigel
title	Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
title_short	Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
title_full	Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
title_fullStr	Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
title_full_unstemmed	Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
title_sort	radiation-tolerant all-digital pll/cdr with varactorless lc dco in 65 nm cmos
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/876fa46e37a041b690ea5a9954a41008
work_keys_str_mv	AT stefanbiereigel radiationtolerantalldigitalpllcdrwithvaractorlesslcdcoin65nmcmos AT szymonkulis radiationtolerantalldigitalpllcdrwithvaractorlesslcdcoin65nmcmos AT paulomoreira radiationtolerantalldigitalpllcdrwithvaractorlesslcdcoin65nmcmos AT alexanderkolpin radiationtolerantalldigitalpllcdrwithvaractorlesslcdcoin65nmcmos AT paulleroux radiationtolerantalldigitalpllcdrwithvaractorlesslcdcoin65nmcmos AT jeffreyprinzie radiationtolerantalldigitalpllcdrwithvaractorlesslcdcoin65nmcmos
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Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

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