Design of universal convolutional layer IP core based on FPGA

Aiming at the problems of insufficient computing speed and poor portability in the miniaturization and parallelization of convolutional neural network,this paper proposes a design of high-speed universal convolutional layer IP core using VHDL language based on the characteristics of convolutional ne...

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Autores principales:	Guochen AN, Hongtuo YUAN, Xiulu HAN, Xiaojun WANG, Yujia HOU
Formato:	article
Lenguaje:	ZH
Publicado:	Hebei University of Science and Technology 2021
Materias:	integrated circuit technology; convolutional neural network; fpga; convolution layer; design parameterization Technology T
Acceso en línea:	https://doaj.org/article/8b62227a47d046a5af79d9621ec59363
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spelling	oai:doaj.org-article:8b62227a47d046a5af79d9621ec593632021-11-23T07:08:47ZDesign of universal convolutional layer IP core based on FPGA1008-154210.7535/hbkd.2021yx03005https://doaj.org/article/8b62227a47d046a5af79d9621ec593632021-06-01T00:00:00Zhttp://xuebao.hebust.edu.cn/hbkjdx/ch/reader/create_pdf.aspx?file_no=b202103005&flag=1&journal_https://doaj.org/toc/1008-1542Aiming at the problems of insufficient computing speed and poor portability in the miniaturization and parallelization of convolutional neural network,this paper proposes a design of high-speed universal convolutional layer IP core using VHDL language based on the characteristics of convolutional neural network and FPGA devices.Layer based on convolution calculation,convolution core design is put forward for the parallel calculation and pipeline module,through each line in the convolution of the core connect to FIFO to improve the data flow,reduce the operating address jump,and join the control core to make it can adjust the convolution with images and convolution window size to layer parameters,generate different convolution layer,finally,the convolution layer is combined with the AXIS protocol and encapsulated into IP core.Under the working frequency of 50 MHz,the convolution calculation of 100×100 images with 2×2 convolution check is carried out.The utilization rate of each resource is less than 1%,[JP2]and the time is 204 μs.The theoretical calculation speed can reach the maximum of 5 MF/s.[JP]The IP core structure of the convolutional layer not only increases the portability of the convolutional module,but also ensures the computing speed,which provides a feasible implementation method for the implementation of convolutional neural network on miniaturized devices.Guochen ANHongtuo YUANXiulu HANXiaojun WANGYujia HOUHebei University of Science and Technologyarticleintegrated circuit technology; convolutional neural network; fpga; convolution layer; design parameterizationTechnologyTZHJournal of Hebei University of Science and Technology, Vol 42, Iss 3, Pp 241-247 (2021)
institution	DOAJ
collection	DOAJ
language	ZH
topic	integrated circuit technology; convolutional neural network; fpga; convolution layer; design parameterization Technology T
spellingShingle	integrated circuit technology; convolutional neural network; fpga; convolution layer; design parameterization Technology T Guochen AN Hongtuo YUAN Xiulu HAN Xiaojun WANG Yujia HOU Design of universal convolutional layer IP core based on FPGA
description	Aiming at the problems of insufficient computing speed and poor portability in the miniaturization and parallelization of convolutional neural network,this paper proposes a design of high-speed universal convolutional layer IP core using VHDL language based on the characteristics of convolutional neural network and FPGA devices.Layer based on convolution calculation,convolution core design is put forward for the parallel calculation and pipeline module,through each line in the convolution of the core connect to FIFO to improve the data flow,reduce the operating address jump,and join the control core to make it can adjust the convolution with images and convolution window size to layer parameters,generate different convolution layer,finally,the convolution layer is combined with the AXIS protocol and encapsulated into IP core.Under the working frequency of 50 MHz,the convolution calculation of 100×100 images with 2×2 convolution check is carried out.The utilization rate of each resource is less than 1%,[JP2]and the time is 204 μs.The theoretical calculation speed can reach the maximum of 5 MF/s.[JP]The IP core structure of the convolutional layer not only increases the portability of the convolutional module,but also ensures the computing speed,which provides a feasible implementation method for the implementation of convolutional neural network on miniaturized devices.
format	article
author	Guochen AN Hongtuo YUAN Xiulu HAN Xiaojun WANG Yujia HOU
author_facet	Guochen AN Hongtuo YUAN Xiulu HAN Xiaojun WANG Yujia HOU
author_sort	Guochen AN
title	Design of universal convolutional layer IP core based on FPGA
title_short	Design of universal convolutional layer IP core based on FPGA
title_full	Design of universal convolutional layer IP core based on FPGA
title_fullStr	Design of universal convolutional layer IP core based on FPGA
title_full_unstemmed	Design of universal convolutional layer IP core based on FPGA
title_sort	design of universal convolutional layer ip core based on fpga
publisher	Hebei University of Science and Technology
publishDate	2021
url	https://doaj.org/article/8b62227a47d046a5af79d9621ec59363
work_keys_str_mv	AT guochenan designofuniversalconvolutionallayeripcorebasedonfpga AT hongtuoyuan designofuniversalconvolutionallayeripcorebasedonfpga AT xiuluhan designofuniversalconvolutionallayeripcorebasedonfpga AT xiaojunwang designofuniversalconvolutionallayeripcorebasedonfpga AT yujiahou designofuniversalconvolutionallayeripcorebasedonfpga
_version_	1718416894191468544

Design of universal convolutional layer IP core based on FPGA

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