A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC

This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time...

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Autores principales:	Suping Bai, Zhi Wan, Peiyuan Wan, Hongda Zhang, Yongkuo Ma, Xiaoyu Zhang, Xu Liu, Zhijie Chen
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	analog-to-digital converter (ADC) hybrid-domain quantization high speed voltage-to-time converter (VTC) time-to-digital converter (TDC) Electronics TK7800-8360
Acceso en línea:	https://doaj.org/article/982fb08a11f44c34bb2a4a4155d0210d
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spelling	oai:doaj.org-article:982fb08a11f44c34bb2a4a4155d0210d2021-11-11T15:39:16ZA 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC10.3390/electronics102126502079-9292https://doaj.org/article/982fb08a11f44c34bb2a4a4155d0210d2021-10-01T00:00:00Zhttps://www.mdpi.com/2079-9292/10/21/2650https://doaj.org/toc/2079-9292This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures the linearity is not sacrificed; the segmented time-to-digital converter (STDC), which further improves the linearity of time domain quantization. The prototype ADC is simulated in a standard 65-nm CMOS process with an active area of 0.038 mm<sup>2</sup>. The simulated SNDR and SFDR are 44.3 and 58 dB with a sampling rate of 1 GS/s. The FoMW and FoMS are 24.7 fJ/conv-step and 150.7 dB, respectively.Suping BaiZhi WanPeiyuan WanHongda ZhangYongkuo MaXiaoyu ZhangXu LiuZhijie ChenMDPI AGarticleanalog-to-digital converter (ADC)hybrid-domain quantizationhigh speedvoltage-to-time converter (VTC)time-to-digital converter (TDC)ElectronicsTK7800-8360ENElectronics, Vol 10, Iss 2650, p 2650 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	analog-to-digital converter (ADC) hybrid-domain quantization high speed voltage-to-time converter (VTC) time-to-digital converter (TDC) Electronics TK7800-8360
spellingShingle	analog-to-digital converter (ADC) hybrid-domain quantization high speed voltage-to-time converter (VTC) time-to-digital converter (TDC) Electronics TK7800-8360 Suping Bai Zhi Wan Peiyuan Wan Hongda Zhang Yongkuo Ma Xiaoyu Zhang Xu Liu Zhijie Chen A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
description	This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures the linearity is not sacrificed; the segmented time-to-digital converter (STDC), which further improves the linearity of time domain quantization. The prototype ADC is simulated in a standard 65-nm CMOS process with an active area of 0.038 mm<sup>2</sup>. The simulated SNDR and SFDR are 44.3 and 58 dB with a sampling rate of 1 GS/s. The FoMW and FoMS are 24.7 fJ/conv-step and 150.7 dB, respectively.
format	article
author	Suping Bai Zhi Wan Peiyuan Wan Hongda Zhang Yongkuo Ma Xiaoyu Zhang Xu Liu Zhijie Chen
author_facet	Suping Bai Zhi Wan Peiyuan Wan Hongda Zhang Yongkuo Ma Xiaoyu Zhang Xu Liu Zhijie Chen
author_sort	Suping Bai
title	A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
title_short	A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
title_full	A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
title_fullStr	A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
title_full_unstemmed	A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
title_sort	9-bit 1-gs/s hybrid-domain pseudo-pipelined sar adc based on variable gain vtc and segmented tdc
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/982fb08a11f44c34bb2a4a4155d0210d
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A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC

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