Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using <italic>In-Situ</italic> ALD Digital O<sub>3</sub> Treatment
Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. <italic>In-situ</italic> digital O<sub>3</sub> treatment in ALD chamber was adopted on the surface of Ge fin sidewall i...
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| Autores principales: | , , , , , , , , , , , , , , , , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
IEEE
2018
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/a5f5f525abe24ceda9f3e6d0178335bc |
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| Sumario: | Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. <italic>In-situ</italic> digital O<sub>3</sub> treatment in ALD chamber was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. The treatment effects were checked by AFM and C-V measurements. By combining this treatment with optimized microwave annealing, sub-threshold slope and the <inline-formula> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ ON}}/\text{I}_{\mathrm{ OFF}}$ </tex-math></inline-formula> ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low <inline-formula> <tex-math notation="LaTeX">${V}_{D}= 0.6$ </tex-math></inline-formula> V was realized. Finally, simulations on an ideal Ge CMOS inverter were presented. |
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