Analysis and Optimization of Defect Generation Due to Mechanical Stress in High-Density SRAM

Static random-access memory (SRAM) is an essential component for realizing large-scale integration (LSI). The future transition to a 48 V DC supply in datacenters and electric vehicles acting as mobile edge servers will increase the demand for a bipolar-complementary metal-oxide semiconductor-double...

Descripción completa

Guardado en:
Detalles Bibliográficos
Autores principales: Kazunari Ishimaru, Mizuki Tamura, Osamu Fujii
Formato: article
Lenguaje:EN
Publicado: IEEE 2021
Materias:
Acceso en línea:https://doaj.org/article/a7cd4cb446024bef9d857380960ef138
Etiquetas: Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
Descripción
Sumario:Static random-access memory (SRAM) is an essential component for realizing large-scale integration (LSI). The future transition to a 48 V DC supply in datacenters and electric vehicles acting as mobile edge servers will increase the demand for a bipolar-complementary metal-oxide semiconductor-double diffused metal-oxide semiconductor with high-capacity SRAM. When we scaled and optimized an SRAM cell from 130 nm nodes to 90 nm nodes, we observed the generation of crystal defects induced by mechanical stress in the p-channel MOS active area that cannot be explained by previous models. We performed simulations using the finite element method to identify the mechanism. In our results, the edge of the narrow active area showed a large deformation compared to the middle of the active area, which can be attributed to compressive stress from the gate electrode and sidewall. The cell layout and sidewall structure were optimized to suppress this defect generation while satisfying reliability requirements, and the design can be extended to 65 nm nodes.