Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This m...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | article |
| Language: | EN |
| Published: |
MDPI AG
2021
|
| Subjects: | |
| Online Access: | https://doaj.org/article/ba7d2eb2ee1949f5af18969e8295843e |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|