Cita APA (7a ed.)

Yadav, N., Kim, Y., Li, S., & Choi, K. K. (2021). Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements. MDPI AG.

Cita Chicago Style (17a ed.)

Yadav, Nandakishor, Youngbae Kim, Shuai Li, y Kyuwon Ken Choi. Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements. MDPI AG, 2021.

Cita MLA (8a ed.)

Yadav, Nandakishor, et al. Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements. MDPI AG, 2021.