Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This m...

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Autores principales:	Nandakishor Yadav, Youngbae Kim, Shuai Li, Kyuwon Ken Choi
Formato:	article
Lenguaje:	EN
Publicado:	MDPI AG 2021
Materias:	SRAM stability reliability CNN read time write time Electronics TK7800-8360
Acceso en línea:	https://doaj.org/article/ba7d2eb2ee1949f5af18969e8295843e
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id	oai:doaj.org-article:ba7d2eb2ee1949f5af18969e8295843e
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spelling	oai:doaj.org-article:ba7d2eb2ee1949f5af18969e8295843e2021-11-11T15:42:52ZStable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements10.3390/electronics102127242079-9292https://doaj.org/article/ba7d2eb2ee1949f5af18969e8295843e2021-11-01T00:00:00Zhttps://www.mdpi.com/2079-9292/10/21/2724https://doaj.org/toc/2079-9292The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This memory uses multi-port reading and writing operations, which reduces stability and reliability. In this paper, we proposed a self-adaptive 12T SRAM cell to increase the read stability for multi-port operation. The self-adaptive technique increases stability and reliability. We increased the read stability by refreshing the storing node in the read mode of operation. The proposed technique also prevents the bit-interleaving problem. Further, we offered a butterfly-inspired SRAM bank to increase the performance and reduce the power dissipation. The proposed SRAM saves 12% more total power than the state-of-the-art 12T SRAM cell-based SRAM. We improve the write performance by 28.15% compared with the state-of-the-art 12T SRAM design. The total area overhead of the proposed architecture compared to the conventional 6T SRAM cell-based SRAM is only 1.9 times larger than the 6T SRAM cell.Nandakishor YadavYoungbae KimShuai LiKyuwon Ken ChoiMDPI AGarticleSRAMstabilityreliabilityCNNread timewrite timeElectronicsTK7800-8360ENElectronics, Vol 10, Iss 2724, p 2724 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	SRAM stability reliability CNN read time write time Electronics TK7800-8360
spellingShingle	SRAM stability reliability CNN read time write time Electronics TK7800-8360 Nandakishor Yadav Youngbae Kim Shuai Li Kyuwon Ken Choi Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
description	The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This memory uses multi-port reading and writing operations, which reduces stability and reliability. In this paper, we proposed a self-adaptive 12T SRAM cell to increase the read stability for multi-port operation. The self-adaptive technique increases stability and reliability. We increased the read stability by refreshing the storing node in the read mode of operation. The proposed technique also prevents the bit-interleaving problem. Further, we offered a butterfly-inspired SRAM bank to increase the performance and reduce the power dissipation. The proposed SRAM saves 12% more total power than the state-of-the-art 12T SRAM cell-based SRAM. We improve the write performance by 28.15% compared with the state-of-the-art 12T SRAM design. The total area overhead of the proposed architecture compared to the conventional 6T SRAM cell-based SRAM is only 1.9 times larger than the 6T SRAM cell.
format	article
author	Nandakishor Yadav Youngbae Kim Shuai Li Kyuwon Ken Choi
author_facet	Nandakishor Yadav Youngbae Kim Shuai Li Kyuwon Ken Choi
author_sort	Nandakishor Yadav
title	Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
title_short	Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
title_full	Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
title_fullStr	Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
title_full_unstemmed	Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
title_sort	stable, low power and bit-interleaving aware sram memory for multi-core processing elements
publisher	MDPI AG
publishDate	2021
url	https://doaj.org/article/ba7d2eb2ee1949f5af18969e8295843e
work_keys_str_mv	AT nandakishoryadav stablelowpowerandbitinterleavingawaresrammemoryformulticoreprocessingelements AT youngbaekim stablelowpowerandbitinterleavingawaresrammemoryformulticoreprocessingelements AT shuaili stablelowpowerandbitinterleavingawaresrammemoryformulticoreprocessingelements AT kyuwonkenchoi stablelowpowerandbitinterleavingawaresrammemoryformulticoreprocessingelements
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Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

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