Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This m...
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| Auteurs principaux: | , , , |
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| Format: | article |
| Langue: | EN |
| Publié: |
MDPI AG
2021
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| Accès en ligne: | https://doaj.org/article/ba7d2eb2ee1949f5af18969e8295843e |
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