Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication

Abstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter u...

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Autores principales:	Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S
Formato:	article
Lenguaje:	EN
Publicado:	Wiley 2021
Materias:	Computer engineering. Computer hardware TK7885-7895 Electronic computers. Computer science QA75.5-76.95
Acceso en línea:	https://doaj.org/article/bdef7fe206c14673bb77006988bfdbfd
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spelling	oai:doaj.org-article:bdef7fe206c14673bb77006988bfdbfd2021-11-17T13:28:44ZEfficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication1751-861X1751-860110.1049/cdt2.12002https://doaj.org/article/bdef7fe206c14673bb77006988bfdbfd2021-01-01T00:00:00Zhttps://doi.org/10.1049/cdt2.12002https://doaj.org/toc/1751-8601https://doaj.org/toc/1751-861XAbstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re‐ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16‐bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.Hemanth Krishna L.Neeharika M.Vishvanath JanjiralaSreehari VeeramachaneniNoor Mahammad SWileyarticleComputer engineering. Computer hardwareTK7885-7895Electronic computers. Computer scienceQA75.5-76.95ENIET Computers & Digital Techniques, Vol 15, Iss 1, Pp 12-19 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Computer engineering. Computer hardware TK7885-7895 Electronic computers. Computer science QA75.5-76.95
spellingShingle	Computer engineering. Computer hardware TK7885-7895 Electronic computers. Computer science QA75.5-76.95 Hemanth Krishna L. Neeharika M. Vishvanath Janjirala Sreehari Veeramachaneni Noor Mahammad S Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
description	Abstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re‐ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16‐bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.
format	article
author	Hemanth Krishna L. Neeharika M. Vishvanath Janjirala Sreehari Veeramachaneni Noor Mahammad S
author_facet	Hemanth Krishna L. Neeharika M. Vishvanath Janjirala Sreehari Veeramachaneni Noor Mahammad S
author_sort	Hemanth Krishna L.
title	Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
title_short	Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
title_full	Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
title_fullStr	Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
title_full_unstemmed	Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
title_sort	efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
publisher	Wiley
publishDate	2021
url	https://doaj.org/article/bdef7fe206c14673bb77006988bfdbfd
work_keys_str_mv	AT hemanthkrishnal efficientdesignof154counterusinganovel53counterforhighspeedmultiplication AT neeharikam efficientdesignof154counterusinganovel53counterforhighspeedmultiplication AT vishvanathjanjirala efficientdesignof154counterusinganovel53counterforhighspeedmultiplication AT sreehariveeramachaneni efficientdesignof154counterusinganovel53counterforhighspeedmultiplication AT noormahammads efficientdesignof154counterusinganovel53counterforhighspeedmultiplication
_version_	1718425570495168512

Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication

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