Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
Abstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter u...
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| Autores principales: | , , , , |
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| Formato: | article |
| Lenguaje: | EN |
| Publicado: |
Wiley
2021
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| Materias: | |
| Acceso en línea: | https://doaj.org/article/bdef7fe206c14673bb77006988bfdbfd |
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