Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects...

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Autores principales:	Longda Zhou, Qianqian Liu, Hong Yang, Zhigang Ji, Hao Xu, Guilei Wang, Eddy Simoen, Haojie Jiang, Ying Luo, Zhenzhen Kong, Guobin Bai, Jun Luo, Huaxiang Yin, Chao Zhao, Wenwu Wang
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	Reliability negative-bias temperature instability (NBTI) Si p-FinFETs post-metallization annealing ALD W gate-filling metal trap generation Electrical engineering. Electronics. Nuclear engineering TK1-9971
Acceso en línea:	https://doaj.org/article/c5b752e8b8c341c8ae304cdcd783f0ac
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spelling	oai:doaj.org-article:c5b752e8b8c341c8ae304cdcd783f0ac2021-11-19T00:01:54ZAlleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization2168-673410.1109/JEDS.2021.3057662https://doaj.org/article/c5b752e8b8c341c8ae304cdcd783f0ac2021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9349750/https://doaj.org/toc/2168-6734In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift (<inline-formula> <tex-math notation="LaTeX">${\Delta }$ </tex-math></inline-formula> <italic>V</italic><inline-formula> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula>), pre-existing traps (<inline-formula> <tex-math notation="LaTeX">${\Delta } {N} _{\mathrm {HT}}$ </tex-math></inline-formula>), generated traps, and their relative contributions were studied. The time exponents of <inline-formula> <tex-math notation="LaTeX">${\Delta }$ </tex-math></inline-formula> <italic>V</italic><inline-formula> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula>, the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B<sub>2</sub>H<sub>6</sub>-based W-filling metal, a 34% reduction in the fresh interface states, reduced <inline-formula> <tex-math notation="LaTeX">${\Delta }$ </tex-math></inline-formula> <italic>V</italic><inline-formula> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula>, and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of <inline-formula> <tex-math notation="LaTeX">${\Delta } {N} _{\mathrm {HT}}$ </tex-math></inline-formula> is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.Longda ZhouQianqian LiuHong YangZhigang JiHao XuGuilei WangEddy SimoenHaojie JiangYing LuoZhenzhen KongGuobin BaiJun LuoHuaxiang YinChao ZhaoWenwu WangIEEEarticleReliabilitynegative-bias temperature instability (NBTI)Si p-FinFETspost-metallization annealingALD W gate-filling metaltrap generationElectrical engineering. Electronics. Nuclear engineeringTK1-9971ENIEEE Journal of the Electron Devices Society, Vol 9, Pp 229-235 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Reliability negative-bias temperature instability (NBTI) Si p-FinFETs post-metallization annealing ALD W gate-filling metal trap generation Electrical engineering. Electronics. Nuclear engineering TK1-9971
spellingShingle	Reliability negative-bias temperature instability (NBTI) Si p-FinFETs post-metallization annealing ALD W gate-filling metal trap generation Electrical engineering. Electronics. Nuclear engineering TK1-9971 Longda Zhou Qianqian Liu Hong Yang Zhigang Ji Hao Xu Guilei Wang Eddy Simoen Haojie Jiang Ying Luo Zhenzhen Kong Guobin Bai Jun Luo Huaxiang Yin Chao Zhao Wenwu Wang Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
description	In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift (<inline-formula> <tex-math notation="LaTeX">${\Delta }$ </tex-math></inline-formula> <italic>V</italic><inline-formula> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula>), pre-existing traps (<inline-formula> <tex-math notation="LaTeX">${\Delta } {N} _{\mathrm {HT}}$ </tex-math></inline-formula>), generated traps, and their relative contributions were studied. The time exponents of <inline-formula> <tex-math notation="LaTeX">${\Delta }$ </tex-math></inline-formula> <italic>V</italic><inline-formula> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula>, the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B<sub>2</sub>H<sub>6</sub>-based W-filling metal, a 34% reduction in the fresh interface states, reduced <inline-formula> <tex-math notation="LaTeX">${\Delta }$ </tex-math></inline-formula> <italic>V</italic><inline-formula> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula>, and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of <inline-formula> <tex-math notation="LaTeX">${\Delta } {N} _{\mathrm {HT}}$ </tex-math></inline-formula> is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.
format	article
author	Longda Zhou Qianqian Liu Hong Yang Zhigang Ji Hao Xu Guilei Wang Eddy Simoen Haojie Jiang Ying Luo Zhenzhen Kong Guobin Bai Jun Luo Huaxiang Yin Chao Zhao Wenwu Wang
author_facet	Longda Zhou Qianqian Liu Hong Yang Zhigang Ji Hao Xu Guilei Wang Eddy Simoen Haojie Jiang Ying Luo Zhenzhen Kong Guobin Bai Jun Luo Huaxiang Yin Chao Zhao Wenwu Wang
author_sort	Longda Zhou
title	Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
title_short	Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
title_full	Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
title_fullStr	Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
title_full_unstemmed	Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization
title_sort	alleviation of negative-bias temperature instability in si p-finfets with ald w gate-filling metal by annealing process optimization
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/c5b752e8b8c341c8ae304cdcd783f0ac
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Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

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