An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors

This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integ...

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Autores principales:	Daehyun Kim, Edward Lee, Jamin Seo, Jinwoo Kim, Sung Kyu Lim, Saibal Mukhopadhyay
Formato:	article
Lenguaje:	EN
Publicado:	IEEE 2021
Materias:	CNFET memory compiler monolithic-3-D (M3D) electronic design automation (EDA) SRAM Computer engineering. Computer hardware TK7885-7895
Acceso en línea:	https://doaj.org/article/df1b2c62224146cda435cc567414f305
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spelling	oai:doaj.org-article:df1b2c62224146cda435cc567414f3052021-11-18T00:11:26ZAn SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors2329-923110.1109/JXCDC.2021.3120715https://doaj.org/article/df1b2c62224146cda435cc567414f3052021-01-01T00:00:00Zhttps://ieeexplore.ieee.org/document/9576728/https://doaj.org/toc/2329-9231This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integrate multiple subarrays of different dimensions to generate larger capacity SRAM arrays. The compiler is demonstrated in a commercial-grade M3D process design kit (PDK) with two tiers of carbon nanotube transistors (CNFETs). Simulations show that the M3D CNT SRAM design can improve the properties of memory compared to the 2-D CNT SRAM design. In a 32-kB memory implementation, the M3D design can reduce footprint, latency, and energy by 33%, 10%, and 19%, respectively. The compiler is used to show the feasibility of fine-grain logic and SRAM stacking in M3D technology.Daehyun KimEdward LeeJamin SeoJinwoo KimSung Kyu LimSaibal MukhopadhyayIEEEarticleCNFETmemory compilermonolithic-3-D (M3D)electronic design automation (EDA)SRAMComputer engineering. Computer hardwareTK7885-7895ENIEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 7, Iss 2, Pp 106-114 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	CNFET memory compiler monolithic-3-D (M3D) electronic design automation (EDA) SRAM Computer engineering. Computer hardware TK7885-7895
spellingShingle	CNFET memory compiler monolithic-3-D (M3D) electronic design automation (EDA) SRAM Computer engineering. Computer hardware TK7885-7895 Daehyun Kim Edward Lee Jamin Seo Jinwoo Kim Sung Kyu Lim Saibal Mukhopadhyay An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors
description	This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integrate multiple subarrays of different dimensions to generate larger capacity SRAM arrays. The compiler is demonstrated in a commercial-grade M3D process design kit (PDK) with two tiers of carbon nanotube transistors (CNFETs). Simulations show that the M3D CNT SRAM design can improve the properties of memory compared to the 2-D CNT SRAM design. In a 32-kB memory implementation, the M3D design can reduce footprint, latency, and energy by 33%, 10%, and 19%, respectively. The compiler is used to show the feasibility of fine-grain logic and SRAM stacking in M3D technology.
format	article
author	Daehyun Kim Edward Lee Jamin Seo Jinwoo Kim Sung Kyu Lim Saibal Mukhopadhyay
author_facet	Daehyun Kim Edward Lee Jamin Seo Jinwoo Kim Sung Kyu Lim Saibal Mukhopadhyay
author_sort	Daehyun Kim
title	An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors
title_short	An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors
title_full	An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors
title_fullStr	An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors
title_full_unstemmed	An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors
title_sort	sram compiler for monolithic-3-d integrated circuit with carbon nanotube transistors
publisher	IEEE
publishDate	2021
url	https://doaj.org/article/df1b2c62224146cda435cc567414f305
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An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors

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