An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors
This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integ...
Guardado en:
Autores principales: | Daehyun Kim, Edward Lee, Jamin Seo, Jinwoo Kim, Sung Kyu Lim, Saibal Mukhopadhyay |
---|---|
Formato: | article |
Lenguaje: | EN |
Publicado: |
IEEE
2021
|
Materias: | |
Acceso en línea: | https://doaj.org/article/df1b2c62224146cda435cc567414f305 |
Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
-
Computing In-Memory Design Based on Double Word Line and Double Threshold 4T SRAM
por: LIN Zhiting, NIU Jianchao+, WU Xiulong, PENG Chunyu
Publicado: (2021) -
Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements
por: Nandakishor Yadav, et al.
Publicado: (2021) -
Analysis and Optimization of Defect Generation Due to Mechanical Stress in High-Density SRAM
por: Kazunari Ishimaru, et al.
Publicado: (2021) -
Monolithic Stacked Dielectric Elastomer Actuators
por: Jun Shintake, et al.
Publicado: (2021) -
EVALUATION OF MONOLITHIC COLUMN FOR INORGANIC MERCURY AND METHYLMERCURY DETERMINATION IN FISH SAMPLE ANALYSIS
por: Bravo,Manuel A., et al.
Publicado: (2018)