Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
Abstract We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy ef...
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| Auteurs principaux: | , , , , , , |
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| Format: | article |
| Langue: | EN |
| Publié: |
Nature Portfolio
2021
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| Sujets: | |
| Accès en ligne: | https://doaj.org/article/f68372b2b4fd4e2db205ac95097f52d8 |
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