Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures

Abstract We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy ef...

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Autores principales:	Sadegh Kamaei, Ali Saeidi, Carlotta Gastaldi, Teodor Rosca, Luca Capua, Matteo Cavalieri, Adrian M. Ionescu
Formato:	article
Lenguaje:	EN
Publicado:	Nature Portfolio 2021
Materias:	Materials of engineering and construction. Mechanics of materials TA401-492 Chemistry QD1-999
Acceso en línea:	https://doaj.org/article/f68372b2b4fd4e2db205ac95097f52d8
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spelling	oai:doaj.org-article:f68372b2b4fd4e2db205ac95097f52d82021-12-02T19:13:48ZGate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures10.1038/s41699-021-00257-62397-7132https://doaj.org/article/f68372b2b4fd4e2db205ac95097f52d82021-09-01T00:00:00Zhttps://doi.org/10.1038/s41699-021-00257-6https://doaj.org/toc/2397-7132Abstract We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 °C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec−1 point subthreshold slope, 20 mV dec−1 average swing over two decades of current, I ON of the order of 100 nA µm−2 and I ON/I OFF > 104 at V d = 1 V. Moreover, an average swing smaller than 10 mV dec−1 over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V−1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.Sadegh KamaeiAli SaeidiCarlotta GastaldiTeodor RoscaLuca CapuaMatteo CavalieriAdrian M. IonescuNature PortfolioarticleMaterials of engineering and construction. Mechanics of materialsTA401-492ChemistryQD1-999ENnpj 2D Materials and Applications, Vol 5, Iss 1, Pp 1-10 (2021)
institution	DOAJ
collection	DOAJ
language	EN
topic	Materials of engineering and construction. Mechanics of materials TA401-492 Chemistry QD1-999
spellingShingle	Materials of engineering and construction. Mechanics of materials TA401-492 Chemistry QD1-999 Sadegh Kamaei Ali Saeidi Carlotta Gastaldi Teodor Rosca Luca Capua Matteo Cavalieri Adrian M. Ionescu Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
description	Abstract We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 °C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec−1 point subthreshold slope, 20 mV dec−1 average swing over two decades of current, I ON of the order of 100 nA µm−2 and I ON/I OFF > 104 at V d = 1 V. Moreover, an average swing smaller than 10 mV dec−1 over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V−1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.
format	article
author	Sadegh Kamaei Ali Saeidi Carlotta Gastaldi Teodor Rosca Luca Capua Matteo Cavalieri Adrian M. Ionescu
author_facet	Sadegh Kamaei Ali Saeidi Carlotta Gastaldi Teodor Rosca Luca Capua Matteo Cavalieri Adrian M. Ionescu
author_sort	Sadegh Kamaei
title	Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
title_short	Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
title_full	Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
title_fullStr	Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
title_full_unstemmed	Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
title_sort	gate energy efficiency and negative capacitance in ferroelectric 2d/2d tfet from cryogenic to high temperatures
publisher	Nature Portfolio
publishDate	2021
url	https://doaj.org/article/f68372b2b4fd4e2db205ac95097f52d8
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Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures

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