Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes

Abstract Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figu...

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Autores principales:	Tarun kumar Agarwal, Bart Soree, Iuliana Radu, Praveen Raghavan, Giuseppe Iannaccone, Gianluca Fiori, Wim Dehaene, Marc Heyns
Formato:	article
Lenguaje:	EN
Publicado:	Nature Portfolio 2017
Materias:	Medicine R Science Q
Acceso en línea:	https://doaj.org/article/3aba0caa895f420b8b71b17ac1ba4519
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spelling	oai:doaj.org-article:3aba0caa895f420b8b71b17ac1ba45192021-12-02T15:06:26ZMaterial-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes10.1038/s41598-017-04055-32045-2322https://doaj.org/article/3aba0caa895f420b8b71b17ac1ba45192017-07-01T00:00:00Zhttps://doi.org/10.1038/s41598-017-04055-3https://doaj.org/toc/2045-2322Abstract Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figure-of-merits (FOMs) e.g. delay, and energy-delay product. In this paper, we present guidelines for 2D material based FETs to meet sub-10 nm high performance logic requirements focusing on material requirement, device design, energy-delay optimization for the first time. We show the need for 2D materials with smaller effective mass in the transport direction and anisotropicity to meet the performance requirement for future technology nodes. We present novel device designs with one such 2D material (monolayer black-phosphorus) to keep Moore’s alive for the HP logic in sub-5 nm gate length regime. With these device proposals we show that below 5 nm gate lengths 2D electrostatistics arising from gate stack design becomes more of a challenge than direct source-to-drain tunneling for 2D material-based FETs. Therefore, it is challenging to meet both delay and energy-delay requirement in sub-5 nm gate length regime without scaling both supply voltage (V DD ) and effective-oxide-thickness (EOT) below 0.5 V and 0.5 nm respectively.Tarun kumar AgarwalBart SoreeIuliana RaduPraveen RaghavanGiuseppe IannacconeGianluca FioriWim DehaeneMarc HeynsNature PortfolioarticleMedicineRScienceQENScientific Reports, Vol 7, Iss 1, Pp 1-7 (2017)
institution	DOAJ
collection	DOAJ
language	EN
topic	Medicine R Science Q
spellingShingle	Medicine R Science Q Tarun kumar Agarwal Bart Soree Iuliana Radu Praveen Raghavan Giuseppe Iannaccone Gianluca Fiori Wim Dehaene Marc Heyns Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
description	Abstract Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figure-of-merits (FOMs) e.g. delay, and energy-delay product. In this paper, we present guidelines for 2D material based FETs to meet sub-10 nm high performance logic requirements focusing on material requirement, device design, energy-delay optimization for the first time. We show the need for 2D materials with smaller effective mass in the transport direction and anisotropicity to meet the performance requirement for future technology nodes. We present novel device designs with one such 2D material (monolayer black-phosphorus) to keep Moore’s alive for the HP logic in sub-5 nm gate length regime. With these device proposals we show that below 5 nm gate lengths 2D electrostatistics arising from gate stack design becomes more of a challenge than direct source-to-drain tunneling for 2D material-based FETs. Therefore, it is challenging to meet both delay and energy-delay requirement in sub-5 nm gate length regime without scaling both supply voltage (V DD ) and effective-oxide-thickness (EOT) below 0.5 V and 0.5 nm respectively.
format	article
author	Tarun kumar Agarwal Bart Soree Iuliana Radu Praveen Raghavan Giuseppe Iannaccone Gianluca Fiori Wim Dehaene Marc Heyns
author_facet	Tarun kumar Agarwal Bart Soree Iuliana Radu Praveen Raghavan Giuseppe Iannaccone Gianluca Fiori Wim Dehaene Marc Heyns
author_sort	Tarun kumar Agarwal
title	Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
title_short	Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
title_full	Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
title_fullStr	Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
title_full_unstemmed	Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes
title_sort	material-device-circuit co-optimization of 2d material based fets for ultra-scaled technology nodes
publisher	Nature Portfolio
publishDate	2017
url	https://doaj.org/article/3aba0caa895f420b8b71b17ac1ba4519
work_keys_str_mv	AT tarunkumaragarwal materialdevicecircuitcooptimizationof2dmaterialbasedfetsforultrascaledtechnologynodes AT bartsoree materialdevicecircuitcooptimizationof2dmaterialbasedfetsforultrascaledtechnologynodes AT iulianaradu materialdevicecircuitcooptimizationof2dmaterialbasedfetsforultrascaledtechnologynodes AT praveenraghavan materialdevicecircuitcooptimizationof2dmaterialbasedfetsforultrascaledtechnologynodes AT giuseppeiannaccone materialdevicecircuitcooptimizationof2dmaterialbasedfetsforultrascaledtechnologynodes AT gianlucafiori materialdevicecircuitcooptimizationof2dmaterialbasedfetsforultrascaledtechnologynodes AT wimdehaene materialdevicecircuitcooptimizationof2dmaterialbasedfetsforultrascaledtechnologynodes AT marcheyns materialdevicecircuitcooptimizationof2dmaterialbasedfetsforultrascaledtechnologynodes
_version_	1718388442943979520

Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes

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