High Pressure Deuterium Passivation of Charge Trapping Layer for Nonvolatile Memory Applications
In this study, the deuterium passivation effect of silicon nitride (Si<sub>3</sub>N<sub>4</sub>) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si<sub>3</sub>N<sub>4<...
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| Auteurs principaux: | , , , , , |
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| Format: | article |
| Langue: | EN |
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MDPI AG
2021
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| Accès en ligne: | https://doaj.org/article/9de899bdf1e04bddb3e48ab30e7ddd08 |
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| Résumé: | In this study, the deuterium passivation effect of silicon nitride (Si<sub>3</sub>N<sub>4</sub>) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si<sub>3</sub>N<sub>4</sub> as a charge trapping layer, deuterium (D<sub>2</sub>) high pressure annealing (HPA) was applied after Si<sub>3</sub>N<sub>4</sub> deposition. Flat band voltage shifts (ΔV<sub>FB</sub>) in data retention mode were compared by CV measurement after D<sub>2</sub> HPA, which shows that the memory window decreases but charge loss in retention mode after program is suppressed. Trap energy distribution based on thermal activated retention model is extracted to compare the trap density of Si<sub>3</sub>N<sub>4</sub>. D<sub>2</sub> HPA reduces the amount of trap densities in the band gap range of 1.06–1.18 eV. SIMS profiles are used to analyze the D<sub>2</sub> profile in Si<sub>3</sub>N<sub>4</sub>. The results show that deuterium diffuses into the Si<sub>3</sub>N<sub>4</sub> and exists up to the Si<sub>3</sub>N<sub>4</sub>-SiO<sub>2</sub> interface region during post-annealing process, which seems to lower the trap density and improve the memory reliability. |
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