Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Abstract This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate...

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Autores principales: Muhammad Fahlesa Fatahilah, Feng Yu, Klaas Strempel, Friedhard Römer, Dario Maradan, Matteo Meneghini, Andrey Bakin, Frank Hohls, Hans Werner Schumacher, Bernd Witzigmann, Andreas Waag, Hutomo Suryo Wasisto
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Publicado: Nature Portfolio 2019
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spelling oai:doaj.org-article:cb21572995a7431785e864b86686240e2021-12-02T15:09:47ZTop-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics10.1038/s41598-019-46186-92045-2322https://doaj.org/article/cb21572995a7431785e864b86686240e2019-07-01T00:00:00Zhttps://doi.org/10.1038/s41598-019-46186-9https://doaj.org/toc/2045-2322Abstract This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (V th) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (ΔV th) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.Muhammad Fahlesa FatahilahFeng YuKlaas StrempelFriedhard RömerDario MaradanMatteo MeneghiniAndrey BakinFrank HohlsHans Werner SchumacherBernd WitzigmannAndreas WaagHutomo Suryo WasistoNature PortfolioarticleMedicineRScienceQENScientific Reports, Vol 9, Iss 1, Pp 1-11 (2019)
institution DOAJ
collection DOAJ
language EN
topic Medicine
R
Science
Q
spellingShingle Medicine
R
Science
Q
Muhammad Fahlesa Fatahilah
Feng Yu
Klaas Strempel
Friedhard Römer
Dario Maradan
Matteo Meneghini
Andrey Bakin
Frank Hohls
Hans Werner Schumacher
Bernd Witzigmann
Andreas Waag
Hutomo Suryo Wasisto
Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
description Abstract This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (V th) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (ΔV th) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.
format article
author Muhammad Fahlesa Fatahilah
Feng Yu
Klaas Strempel
Friedhard Römer
Dario Maradan
Matteo Meneghini
Andrey Bakin
Frank Hohls
Hans Werner Schumacher
Bernd Witzigmann
Andreas Waag
Hutomo Suryo Wasisto
author_facet Muhammad Fahlesa Fatahilah
Feng Yu
Klaas Strempel
Friedhard Römer
Dario Maradan
Matteo Meneghini
Andrey Bakin
Frank Hohls
Hans Werner Schumacher
Bernd Witzigmann
Andreas Waag
Hutomo Suryo Wasisto
author_sort Muhammad Fahlesa Fatahilah
title Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
title_short Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
title_full Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
title_fullStr Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
title_full_unstemmed Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
title_sort top-down gan nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
publisher Nature Portfolio
publishDate 2019
url https://doaj.org/article/cb21572995a7431785e864b86686240e
work_keys_str_mv AT muhammadfahlesafatahilah topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT fengyu topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT klaasstrempel topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT friedhardromer topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT dariomaradan topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT matteomeneghini topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT andreybakin topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT frankhohls topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT hanswernerschumacher topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT berndwitzigmann topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT andreaswaag topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
AT hutomosuryowasisto topdowngannanowiretransistorswithnearlyzerogatehysteresisforparallelverticalelectronics
_version_ 1718387779281354752